—The major drawback of an inverter are Total

Harmonic Distortion (THD) and Harmonics. The study of

harmonics and THD are carried out in this work. The

cascaded multilevel inverter topology is incorporated to

suppress the harmonics produced by the inverter at its output.

The cascaded multilevel inverter is most effective with fuel cells or battery stored power. The cells have low voltage ratings, the cascaded inverter input must be of low voltages to achieve 230v output. The simulation work is carried out with simulink/matlab. The harmonics at output of inverter with 3 phase load is studied. 3 level and 5 level cascaded multilevel inverter’s harmonics and THD are compared with traditional inverter drive. The study of multilevel inverter topology

suppresses the harmonics and THD

Manjesh, .

Rajesh, B.

ePrints@Bangalore University

2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]  Comparison of Harmonics and THD Suppression with Three and 5 Level Multilevel Inverter-Cascaded H-bridge Rajesh B Department of Electronic Science  Bangalore University Bengaluru rajeshb0201@gmail.com  Dr Manjesh Department of Electronic Science Bangalore University Bengaluru  manjesh1972@gmail.com   Abstract—The major drawback of an inverter are Total Harmonic Distortion (THD) and Harmonics. The study of harmonics and THD are carried out in this work. The cascaded multilevel inverter topology is incorporated to suppress the harmonics produced by the inverter at its output. The cascaded multilevel inverter is most effective with fuel cells or battery stored power. The cells have low voltage ratings, the cascaded inverter input must be of low voltages to achieve 230v output. The simulation work is carried out with simulink/matlab. The harmonics at output of inverter with 3 phase load is studied. 3 level and 5 level cascaded multilevel inverter’s harmonics and THD are compared with traditional inverter drive. The study of multilevel inverter topology suppresses the harmonics and THD.  Keywords— Cascaded inverter, Multilevel inverter, there level inverter, five level inverter, harmonics, THD. I.  INTRODUCTION  The Traditional inverter drive or two level inverter drive is the commonly used basic inverter drive. The property of  inverter to produce harmonics, the harmonics will cause the power electronic system or a load to heat up and reduce the life of the device. These harmonics are to be removed or be suppressed, the most basic or primitive measure to eliminate harmonics is to introduce filters between load and inverter. The filters are capacitors and inductors connected in different topologies, these filters are bulky and expensive. It complex to design and construct the exact desired filters. The issue of these filters introducing delay has to accounted , for the high voltage and high power applications multilevel(ML)inverters are a promising inverter topology[1 2]. Several different levels of DC voltages are produced by this type of inverter to produce a stepped AC output that is almost the pure sine wave. Multilevel has the advantages of higher efficiency, lower switching losses and switching frequency, high power quality waveforms, reduced dv/dt stress, very low harmonic distortion lower voltage ratings of devices, etc. In comparison with 2 level inverter multilevel gives more reliability with low speed. [3]. The multilevel inverter will suppress the harmonics which will reduce the filter bulkiness and expense. The switching devices are to be switched on and off in a particular pattern that the multilevel output produced using different DC levels to obtain output AC voltage, the desired fundamental voltage is obtained with elimination of several number of harmonics of higher order which will result in harmonics distortion at its least amount in the output of AC voltage [4-5]. The multilevel inverter topology (cascaded) is used to suppress the harmonics in this paper. 3 level and 5level inverter topology is used for the simulation work. The concept of H-bridge inverters is to be connected  in series to obtain a sinusoidal voltage output. The voltage generated at the output is the sum generated by each cell. 2n+1 output voltages levels are generated, n denotes the number of cells. The cascaded ML inverter has the advantage of using less number of components compared to flying capacitor ML or Diode clamped, this implies that the inverter weight is less than of the former two types. The switching devices for required for an n level cascaded H-bridge multilevel inverter is 2(n-1) where n signifies the number of output voltage levels. The demand for renewable energy system in the current global climate has increased due to limited fossil resources and environmental issues [6 7 8]. The most common type of grid connected renewable energy system is the photovoltaic system. The challenging work is match the output voltage and frequency, to connect these system to the grid. In Photo-Voltaic (PV) or Fuel Cell (FC) applications, coppers are used to buck or boost the variable and lower quality output voltage of the fuel cells or PV panels. The desired voltage and frequency can be implemented to the grid connection with an inverter. A multilevel inverter enables renewable energy sources to be used because it can achieve high power ratings. The switching components voltage rating is not increased when multilevel inverter output voltage is to be  increased. For static var generation applications cascaded multilevel inverters are proposed as a renewable energy source interface, and for applications which are battery-based. These inverters offer direct connection of renewable energy system to the grid without using the bulky and heavy transformers and expensive [9 10 11]. The many level Identify applicable sponsor/s here. If no sponsors, delete this text box (sponsors). 978-1-5090-1277-0/16/$31.00 ©2016 IEEE 2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]    inverters output voltage is a staircase which is more towards sinusoidal voltage using DC link voltages compared with traditional inverter. The generation of stepped output voltage allows harmonic content to be suppressed resulting in the output filter size to be reduced. The induction motor is used as load in this paper. The induction motor consumes 40% of the electricity produced, in all applications the speed of the motor is not at the rated speed. The most used control method is v/f method where frequency and voltage are varied to obtain the desired speed of the motor[12]. The same has been done in this paper the motor is run at frequency of 7Hz and the simulation results are obtained.  II. TRADITIONAL INVERTER DRIVE  The traditional inverter drive consists of six switches. Fig.1 shows the circuit layout of the three phase traditional inverter drive (TID). The switches used are IGBT’s, the pulse generator provides the required gating. Each phase has  1200 phase difference. The Sb1 is switched on with a phase lag of 1200 with respect Sa1, similarly Sc1 is switched on with a phase lag of 120° with respect Sb1. The switches Sb1, Sc1 and Sa1 are the upper switches and switches Sb2, Sc2 and Sa2 are the lower switches. All the lower switches are the compliments of their respective upper switch. Sa1, Sb1 and Sc1are the compliments of Sa2, Sb2 and Sc2 respectively. The switches in the same leg should not be ON simultaneously. The pattern of switching is two from upper group and one form the lower group or two from lower group and one from upper group are ON. This results in a 3 phase output power used to drive the motor.   Fig.1. Traditional inverter drive with motor load. III. MULTI-LEVEL INVERTER DRIVES: A. Three Level H-bridge Cascaded Multilevel Inverter Dirve The Three level H-bride cascaded inverter drive has 8 switches. The Fig .2 shows the circuit layout of phase ‘a’ of three level inverter drive. The switches used are IGBT’s, the pulse generator provides the required gating. Each phase has 1200 phase difference. The switches Sa1and Sa4 have the same pulse input so does switches Sa2and Sa3, Sa5 and Sa8, Sa6 and Sa7.The switches Sa1,Sa2,Sa3 and Sa4 are turned on with a delay of 100 with reference to switches Sa5,Sa6,Sa7 and Sa8 respectively and are ON for a duration of 1600. Sa1, Sa3, Sa5 and Sa7 are the upper switches and switches Sa2, Sa4, Sa6 and  Sa8 are the lower switches. All the lower switches are the compliments of their respective upper switch, The switches in the same leg should not be ON simultaneously. The pattern of switching is two from upper group and one form the lower group or two from lower group and one from upper group are ON. This results in a 3 phase output power used to drive the motor.The timing signal for phase ‘b’ and ‘c’ are same as phase ‘a’ but with 1200 phase delay. i.e., phase ‘b’ is 1200 out of phase from phase ‘a’ and phase ‘c’ is 1200 out of phase from phase ‘b’.  Fig.2. Phase a of three level cascaded H-bridge multilevel inverter  B. Five level cascaded H-bridge Multilevel Inverter Drive The five level cascaded H-bride inverter drive has 8 switches. The Fig.3 shows the circuit diagram of phase ‘a’ of three level inverter drive. The switches used are IGBT’s, the pulse generator provides the required gating. Each phase has 1200 phase difference.  The switches Sa1and Sa4 have the same pulse input so does switches Sa2and Sa3, Sa5 and Sa8, Sa6 and Sa7, Sa9 and Sa12, Sa10 and Sa11.The switches Sa1,Sa2,Sa3 and Sa4 are turned on with a delay of 100 with reference to switches Sa5,Sa6,Sa7 and Sa8 respectively and are ON for a duration of 1400. The switches Sa5, Sa6, Sa7 and Sa8 are turned on with a delay of 100 with reference to switches Sa9, Sa10, Sa11 and Sa12 respectively 2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]    and are ON for a duration of 1600. Sa1, Sa3, Sa5, Sa7, Sa9 and Sa11 are the upper switches and switches Sa2, Sa4, Sa6, Sa8, Sa10 and Sa12 are the lower switches. All the lower switches are the compliments of their respective upper switch. The switches in the same leg should not be ON simultaneously. The pattern of switching is two from upper group and one form the lower group or two from lower group and one from upper group are ON.  This results in a 3 phase output power used to drive the motor.The timing signal for phase ‘b’ and ‘c’ are same as phase ‘a’ but with 1200 phase delay. i.e., phase ‘b’ is 1200 out of phase from phase ‘a’ and phase ‘c’ is 1200  out of phase from phase ‘b’.   Fig.3. Phase a of five level H-bridge cascaded ML inverter   IV. RESULTS  The simulation of above circuits is carried out with simulink/Matlab. The following results are obtained. Fig.4 and Fig .5 gives the output waveform of stator voltage and line current with traditional inverter drive(TID) respectively. The timing signal are designed for a frequency of 7hz.   Fig.4. Stator Voltage waveform of the motor with TID.   Fig.5. Line Current waveform of the motor with TID.  Fig.6 & Fig .7 gives the output waveform of stator voltage and line current with three level H-bridge cascaded ML inverter drive respectively.   Fig.6. Stator Voltage waveform of the motor with 3 level H-bridge cascaded ML inverter.  2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]     Fig.7. Line Current waveform of the motor with 3 level cascaded H-bridge Fig.8 & Fig .9 shows the output waveform of stator voltage and line current with five level H-bridge cascaded multilevel inverter drive respectively.   Fig.8. Stator voltage waveform of the motor with 5 level H-bridge cascade.  Fig.9. Stator waveform of the motor with 5 level H-bridge cascade.  Fig .10, Fig.11 and Fig.12 shows the harmonics bar graph and THD of stator voltage with traditional inverter drive, 3 level H-bridge cascaded ML and five level H-bridge  cascaded ML inverter drive respectively.    Fig.10. Harmonic profile of Stator voltage of the motor with Traditional inverter drive.   Fig.11. Profile of Harmonic of Stator voltage of the motor with 3 level H-bridge cascade.  Fig.12. Harmonic profile of Stator voltage of the motor with 5 level H-bridge cascade. 2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]    Fig. 13, Fig.14 & Fig. 15 shows the harmonics profile and THD of stator current with traditional inverter drive, three level H-bridge cascaded ML and five level H-bridge cascaded ML inverter drive respectively. Fig.13. Harmonic profile of Stator current of the motor with Traditional inverter drive.  Fig.14. Harmonic profile of Stator current of the motor with 3 level cascaded H-bridge. TABLE I.  TOTAL HARMONIC DISTORTION Type of drive Voltage THD in % Current THD in % Traditional Inverter Drive 31.09 13.56 3-level cascaded H-bridge Drive 26.32 16.09 5-level cascaded H-bridge Drive 15.94 7.21  Table I contains the voltage and current harmonics of all the three drives discussed in this paper. The speed (rpm) of the motor is also noted for all three topologies and they are found to be same in all cases. The rpm varies between 186 to 195. Table II gives the detail harmonic percentages. Fig.16 shows the speed variation with time.  Fig.15. Harmonic profile of Stator current of the motor with 5 level cascaded H-bridge.  Fig.16. rpm v/s time graph. (x-axis, y-axis) TABLE II.  INDIVIDUAL HARMONICS PERCENTAGES OF ALL DRIVES Harmonic no TID vol TID curr 3level vol 3level curr 5level vol 5level curr 1 100 100 100 100 100 100 2 0.01 0.02 16.60 13.24 5.96 0.02 3 0.01 0.02 0 0.01 0 0.02 4 0.01 0.02 12.71 7.31 6.64 0.02 5 19.99 11.17 8.5 4.81 2.14 11.17 6 0 0.01 0 0.01 0 0.01 7 14.3 6.38 1.68 0.78 5.96 6.36 8 0 0.01 2.06 0.93 4.36 0.01 9 0 0.01 0 0 0 0.01 10 0 0.01 1.96 0.61 3.5 0.01 11 9.09 2.98 1.16 0.37 6.04 2.98 12 0 0.01 0 0 0 0.01 13 7.71 2.19 3.4 0.94 2.71 2.19 14 0 0.01 3.74 0.98 1.66 0.01 15 0 0.01 0 0.01 0 0.01 16 0 0.01 2.12 0.49 1.79 0.01 17 5.89 1.32 5.98 1.34 1.87 1.32 18 0 0.01 0 0.01 0 0.01 19 5.29 1.07 5.3 1.08 1.68 1.07 2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]    V. CONCLUSION A traditional three phase induction motor drive is studied for harmonic analysis and THD with simulink/Matlab, and compared the results with the 3-phase 3 level and 3-phase 5 level H-bridge Multilevel inverter drives, the study has been done for an input frequency of 7hz. The results indicates that speed remains constant with all the drives. The voltage harmonics reduces by having more inverter levels. In case of line current the harmonics for traditional and three level remains the same but for 5level H-bridge Multilevel Inverter drive the harmonics is suppressed by half. By this we concluded that by using H-bridge cascaded ML inverter drives the harmonics and THD can be reduced, which will result in reduction of filter bulky components used for the experimental purpose. In further this simulation work is extended experimentally to study the stator temperature of 3-phase induction motor.  REFERENCES  [1] Dhaval Patel, Himanshu N. Chaudhari, Dr. Hina Chandwani, Mr. Anand Damle,“Analysis and Simulation of Asymmetrical Type Multilevel Inverter Using Optimization Angle Control Technique,” IJAEEE, vol. 1, issue. 3, 2012. [2] P. Thongprasri,” A 5-Level Three-Phase Cascaded Hybrid Multilevel Inverter,” International Journal of Computer and Electrical Engineering, pp. 789-794,  Vol. 3, No. 6, December 2011. [3] Murgesan G, Jagabar Sathik M Praveen M, “A new multilevel inverter topology using less number of switches,,” International Journal of Engineering Science and Technology, vol. 3 No. 2, pp. 5000-5010,  Feb 2011. [4] C. Govindaraju, K. Baskaran,”Performance Improvement of Multiphase Multilevel Inverter Using Hybrid Carrier Based Space Vector Modulation,” International Journal on Electrical Engineering and Informatics - vol 2,no 2, pp.137-149, 2010. [5] Rajesh B, Manjesh, ’Study and analysis of THD and content of Harmonics in Three Phase PWM Inverter with Filters,” International Journal of Advance Electrical and Electronics Engineering ,vol. 3 issue. 3, 2014. [6] M.Murugesan, R.Sakthivel, E. Muthukumaran, R.Sivakumar, “ Sinusoidal PWM Based Modified Cascaded Multilevel Inverter,” International Journal Of Computational Engineering Research,vol. 2, issue no. 2, pp.529-539, 2012. [7] Gobinath.K, Mahendran.S, Gnanambal.I, “New cascaded H-bridge multilevel inverter with improved efficiency”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering Vol. 2, Issue 4,pp. 1263-1271,  April 2013. [8] K.Surya Suresh and M.Vishnu Prasad, “PV Cell Based Five Level Inverter Using Multicarrier PWM,” International Journal of Modern Engineering Research, vol.1, issue.2, pp-545-551. [9] Ananda A S, Manjesh, “Analysis and comparison of THD in Five Phase PWM Inverter drive using Resonant Filter,” International Journal of Advance Electrical and Electronics Engineering, vol. 3 issue. 3, 2014 [10] M. Kavitha, A. Arunkumar, N. Gokulnath, S. Arun, “ New Cascaded H-Bridge Multilevel Inverter Topology with Reduced Number of Switches and Sources ,” Journal of Electrical and Electronics Engineering , vol. 2, issue. 6 , pp 26-36, 2012. [11] Dr. Manjesh and Ananda A S, “Study and analysis of THD & Power factor in Single phase Inverter with Flyback Thyristor Converter,” International Journal of Advance Electrical and Electronics Engineering (IJAEEE) ISSN (Print): 2278-8948, Volume-3 Issue-4, Pg 5-8, 2014. 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Comparison of harmonics and THD suppression with three and 5 level multilevel inverter-cascaded H-bridge

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Comparison of harmonics and THD suppression with three and 5 level multilevel inverter-cascaded H-bridge

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