This thesis presents a new design for a 0.18mum CMOS analog Operational Amplifier. The most difficult design challenge for a low-voltage operational amplifier is the design of a rail-to-rail input differential amplifier stage with a constant transconductance (gm). The main contribution in this thesis is the novel design methodology of a DC level shifter that enables the synthesis of a 0.18mum CMOS analog operational amplifier with a constant-gm implementation over a common-mode voltage range from 0 to 1.8V. The design of a 0.18mum CMOS low-voltage operational amplifier with constant overall transconductance gm, which allows for a rail-to-rail input swing without degrading the common-mode rejection ratio (CMRR) or causing the slew rate to vary, is developed in this thesis. The DC level shifter circuit design methodology optimizes all the transistors of the DC level shifter to improve the overlapping of p-pair and n-pair tail currents. The 1.8V CMOS operational amplifier has power consumption less than 178muw, a CMRR of 123.6 dB and a slew rate of 4V/mus. A total of 32 transistors were used in the final layout. The purpose of this design is to build the operational amplifier as an Intellectual Property (IP) core suitable for System-on-Chip (SOC) implementation. This IP core can be repeatedly used in future designs and should also be able to easily inserted into any vendor technology or design methodology. Source: Masters Abstracts International, Volume: 41-04, page: 1155. Adviser: W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2002
