This paper introduces a new polymorphous computing Fabric well suited to DSP and Image Processing and describes its implementation on a Configurable System on a Chip (CSOC). The architecture is highly parameterized and enables customization of the synthesized Fabric to achieve high performance for a specific class of application. For this reason it can be considered to be a generic model for hardware accelerator synthesis from a high level specification. Another important innovation is the Fabric uses a global memory concept, which gives the host processor random access to all the variables and instructions on the Fabric. The Fabric supports different computing models including MIMD, SPMD and systolic flow and permits dynamic reconfiguration. We present a specific implementation of a bank of FIR filters on a Fabric composed of 52 cells on the Altera Excalibur ARM running at 33 MHz. The theoretical performance of this Fabric is 1.8 GMACh. For the FIR application we obtain 1.6 GMAC/s real performance. Some automatic tools have been developed like the tool to provide a host access utility and assembler
