FPGAs are an appealing solution for space-based remote sensing applications. However, an a low-earth orbit, FPGAs are susceptible t o Single-Event Upsets (SEUs). In an effort to understand the effects of SEUs, an SEU simulator based on the SLAAC-1V computing board has been developed. This simulator artifically upsets the conjiguration memory of an FPGA and measures its impact on FPGA designs. The accuracy of this simulation environment has been verified using ground-based radiation testing. This sim{approx}ulataon tool is being used to characterize the reliabilitg of SEU mitigation techniques for PI'GAs
