Future mobile and wireless communications networks
require flexible modem architectures with high performance.
Efficient utilization of
application specific flexibility is key to fulfill these
requirements.
For high throughput a single processor can not provide
the necessary computational power.
Hence multi-processor architectures become necessary.
This paper presents a multi-processor platform based on a new
dynamically reconfigurable application specific instruction set processor (dr-ASIP)
for the application domain of channel decoding.
Inherently parallel decoding tasks can be mapped onto individual processing nodes.
The implied challenging inter-processor communication is efficiently handled
by a Network-on-Chip (NoC) such that the throughput of each node is not degraded.
The dr-ASIP features Viterbi and Log-MAP decoding
for support of convolutional and turbo codes
of more than 10 currently specified mobile and wireless standards.
Furthermore, its flexibility allows for adaptation to future systems
