Large-scale three-dimensional area array electronic packaging analysis

Abstract

[[abstract]]As integrated circuit functionality, performance, and density continue to improve, innovative next-generation packaging approaches are in great demand. The ball grid array (BGA) type packaging technology such as flip chip, plastic/ceramic BGA (PBGA/CBGA), and chip scale packaging are attracting worldwide interest and commitment as the potentially lowest cost package for high-I/O devices and for lower pincount (e.g., Tessera's BGA) applications. Drivers include the I/O density advantages of an area array, the potential for excellent electrical and thermal performance, and so on. However, some of the reliability issues of the BGA type package are not eradicated, and research is critically needed in the area of next-generation electronic package analysis and design (e.g., improvement of package reliability, increase in the assembly yields rate, reduction of the solder bump pitches, etc.). A substructuring such as the local-global finite element method with a multipoint constraints boundary condition is developed for prediction of the fatigue life of the solder joint. This methodology could significantly reduce the CPU time and make the large-scale three-dimensional electronic-packaging analysis possible.[[fileno]]2020233010054[[department]]動機