Author name used in this publication: J. Y. Dai2005-2006 > Academic research: refereed > Publication in refereed journalVersion of RecordPublishe

Dai, J

Lu, XB

Applied Physics Letters

Author name used in this publication: J. Y. Dai2005-2006 > Academic research: refereed > Publication in refereed journalVersion of RecordPublishedVoR allowe

PolyU Institutional Repository

APPLIED PHYSICS LETTERS 88, 113104 2006DownloMemory effects of carbon nanotubes as charge storage nodes for floatinggate memory applicationsX. B. Lu and J. Y. DaiaDepartment of Applied Physics and Materials Research Center, The Hong Kong Polytechnic University,Hung Hom, Kowloon, Hong Kong, People’s Republic of ChinaReceived 11 October 2005; accepted 2 February 2006; published online 14 March 2006A nonvolatile flash memory device has been fabricated using carbon nanotubes CNTs as a floatinggate embedded in HfAlO the atomic ratio of Hf/Al is 1:2 high-k tunneling/control oxides and itsmemory effect has been observed. Capacitance-voltage C-V measurements illustrated a 400 mVmemory window during the double C-V sweep from 3 to −3 V performed at room temperature and1 MHz. Further studies on their programming characteristics revealed that electron is difficult to bewritten into the CNTs and the memory effect of the structures is mainly due to the holes traps. Thememory window width can remain nearly unchanged even after 104 s stressing, indicating excellentlong term charge retention characteristics. We therefore suggest that the CNTs embedded in HfAlOcan be potentially applied to floating gate flash memory devices. © 2006 American Institute ofPhysics. DOI: 10.1063/1.2179374Since their discovery in the early 1990s,1 carbon nano-tubes CNTs have attracted much attention, both of scien-tific and technological interest, for possible nanoelectronicapplications. To date, a number of nanoelectronic deviceshave been realized with CNTs, such as field effecttransistors,2–4 room-temperature single-electron transistors,5logic gate circuits,6 inverters,7 and electromechanicalswitches.8 Very recently, the prototypes of memory devicesbased on CNT field effect transistors were also reported,9–12demonstrating another significant extension of CNTs appli-cations. From then on, several groups have carried out re-search on the CNT-based memories.13–17 In these researchworks, the CNTs were synthesized on a conductive Si sub-strate capped by several hundred nanometers of SiO2. Metalelectrodes were evaporated on the CNTs to form source anddrain electrical contact to them. The conductive Si substrateactually acts as the gate of the memory device. The functionof the CNTs was the current channel, and the memory effectof the devices was attributed to the charges injected from theCNTs to the defects or charge traps in the dielectrics or theinterface between the CNTs and the oxides.15–17 The CNTswere not used as the charge storage nodes.For commonly studied flash memory devices, Si,18 Ge,19and Si1−xGex Ref. 20 nanocrystals are widely used as thecharge storage nodes and the memory structures are sand-wiched with nanocrystals embedded in the SiO2 or high-kdielectrics. But up to now, there is no report on flash memorydevices using CNTs as a floating gate. In terms of electricalproperties, CNTs have many unique advantages for the ap-plication in memory devices such as tunable band gap, highthermal stability and chemical inertness, perfect sidewallstructure, and nearly zero surface states.21,22 These uniqueproperties are very favorable for their application as thecharge storage nodes in the memory devices. In this letter,we report the fabrication of the HfAlO/CNTs/HfAlO/Simemory structures and characterization of the uniquememory characteristics of CNTs using as the charge storagenodes. HfAlO was chosen as the tunneling and control ox-aElectronic mail: apdaijy@inet.polyu.edu.hk0003-6951/2006/8811/113104/3/$23.00 88, 11310aded 22 Aug 2011 to 158.132.161.52. Redistribution subject to AIP licides in the memory structures due to its promising perfor-mance for high-k gate dielectric application23 and floatinggate memory device application.19Before tunneling HfAlO film deposition, the p-Si100substrate with a resistivity of 4–6  cm was first etched by aHF 10% solution for 10 s. Then one very thin layer ofHfAlO film was deposited on the Si substrate by the lasermolecular beam epitaxy MBE technique using a KrF exci-mer laser LPX 205i, Lambda Physik, 248 nm in wave-length, 30 ns in pulse width, operated at 1 Hz. The ratio ofHf to Al for the ceramic target is 1:2. The commercial CNTspurity90%  were synthesized by chemical vapor deposi-tion and their diameter and length are about 2 nm and1.5 m, respectively. The original powder like CNTs werefirst dispersed in the acetone solution by ultrasonic method.The estimated density for CNTs in the acetone is around0.1 mg/ml. After immersing into the CNTs containing ac-etone solution for 10 s, the Si substrate covered with a layerof HfAlO tunneling oxide was pulled out slowly. Finally,another layer of HfAlO was deposited to cover these CNTsand form the structure of HfAlO/CNT/HfAlO/Si. The basevacuum of the laser MBE system before film deposition is210−5 Pa and the oxygen pressure for the deposition ofHfAlO films was 0.2 Pa. The growth rate for the HfAlO filmis about 2 nm/min. To minimize the interfacial reaction be-tween the HfAlO film and the Si substrate, the depositionsubstrate temperature was selected to be 400 °C. A controlsample with only two layers of HfAlO films with the nomi-nal thickness same as the control and tunneling oxide layersof the memory structure was also prepared. To improve theinterfacial quality between the Si substrate and the HfAlOfilm and between the two layers of HfAlO, all the sampleswere in situ annealed in pure N2 ambient at an elevated tem-perature of 700 °C for 30 min. Pt top electrodes with an areaof 3.1410−4 cm2 were deposited on the surface of thesamples using a shadow mask. Finally, back contact of silverwas used to form the metal-oxide-silicon MOS memorystructures. The hysteresis loop and the charge retention char-acteristics of the MOS memory devices were evaluated bycapacitance-voltage C-V and capacitance-time measure-© 2006 American Institute of Physics4-1ense or copyright; see http://apl.aip.org/about/rights_and_permissions113104-2 Lu and Dai Appl. Phys. Lett. 88, 113104 2006Downloments with an Agilent 4294A impedance analyzer at roomtemperature. The cross-sectional structures of the trilayermemory stack were characterized by high-resolution trans-mission electron microscopy HRTEM.The schematic structure of floating gate memory devicesusing CNTs as floating gate is shown in Fig. 1a. The p-typesubstrate is designed as the current channel and the CNTs aredesigned to be embedded in the HfAlO films and act as thecharge storage nodes. Figure 1b shows the cross-sectionalHRTEM images of the actual memory devices, where thebright circle-like regions can be found embedded in theHfAlO film, which are determined to be CNTs. This indi-cates that the HfAlO/CNT/HfAlO/Si memory structureshave been fabricated. It is also apparent that the HfAlO filmremains an amorphous structure even after a 30 min N2 an-nealing at 700 °C.To study the charge trapping effect of the samples,double C-V sweeps were performed at a high frequency of1 MHz at room temperature. The gate voltage was sweptfrom inversion to accumulation to obtain the forward highfrequency C-V characteristics and from the accumulationback to inversion for the reverse C-V characteristics. Figure2 shows the typical C-V hysteresis loops of the samples withand without CNTs. A clear hysteresis between subsequentforward and backward C-V curves can be observed for thesample containing CNTs. During the voltage sweep range of3 to −3 V, a memory window width of 400 mV was ob-served. For the control sample of Pt/HfAlO/Si structures,the backward C-V curve nearly overlaps the forward C-VFIG. 1. Color online a Schematic structure of theHfAlO/CNTs/HfAlO/Si MOS memory structure. and b HRTEM imageof CNTs embedded in HfAlO control and tunneling layers.curve and no clear hysteresis loop can be observed, indicat-aded 22 Aug 2011 to 158.132.161.52. Redistribution subject to AIP licing that the defects and interfacial states between the controland tunneling oxide or HfAlO/Si have been greatly reducedby postannealing in N2 ambient. Therefore, it can be con-cluded that the memory effect of the sample containingCNTs is really due to the incorporation of CNTs into HfAlOdielectrics. This memory window also indicates that a smallnumber of electrons/holes have tunneled into the CNTs andwere stored inside. According to Yoneya et al.’s report,12 theCNTs were also suggested to be the charge storage nodes.However, the memory window of their CNTs based flashmemory devices was observed only at low temperature. Theobservation of room temperature memory effect in our CNTbased memory devices is most likely due to embedding ofCNTs in the HfAlO dielectrics, which makes the trappedcharges in the CNTs difficult to tunnel back to the substratefor the high potential barrier between the CNTs and the tun-neling HfAlO high-k dielectrics.The typical programming characteristics of the fabri-cated CNT based devices under different programming timeare shown in Fig. 3. All the flatband voltages in this figurewere determined from the forward C-V sweep of the voltagerange of 2 to −2 V. A positive voltage is generally consid-ered as the programming voltage for the p-type flashmemory devices using Si, Ge nanocrystals as floating gate.In this letter, a negative charging voltage is also taken for aprogramming voltage. Figure 3 shows that when a program-ming voltage of 5 V was applied to the memory devices, theflatband voltage has little change with the increase of theFIG. 2. Color online Typical C-V hysteresis characteristics of the CNT-based MOS memory devices and the control sample.FIG. 3. Color online Writing characteristics of the MOS memory devicesunder different programming time by +5 and −5 V, respectively.ense or copyright; see http://apl.aip.org/about/rights_and_permissions113104-3 Lu and Dai Appl. Phys. Lett. 88, 113104 2006Downloprogramming time, suggesting that electrons are difficult tobe written into the CNTs even by a long programming time.On the contrary, with the increase of the programming time,a clear increase of the flatband voltage shift can be observedfor a negative programming voltage of −5 V, indicating thatholes are much easier to be written into the CNTs and areresponsible for the memory effect of this kind of memorydevices. This result is consistent with the assumption on thehole trapping into the CNTs proposed by Yoneya et al.12The charge retention characteristics of the CNTs basedmemory devices were measured at room temperature after acharging voltage of ±5 V was applied for 1 s. As shown inFig. 4, the capacitance at the bias voltage of −0.5 V, which isnear the flatband point, were monitored as a function of thestressing time. The charge retention characteristics can bedivided into two stages. In the first stage, the memory win-dow of capacitance significantly narrows within the first102 s. This quick decrease of the memory window may bedue to the lateral charge loss between the CNTs in our struc-tures. Because it is difficult to separate all the CNTs intoindividual CNT, there always exist some bundles of CNTs orconnections between one CNT with another one in neighbor-ing MOS memory devices. Another stage is the long termretention stage. In this stage, excellent long term charge re-tention characteristics can be observed. The width of thememory window remains nearly unchanged even after 104 sstressing.To explain the excellent charge retention characteristics,we propose the following mechanisms. First, we believe thatthe excellent retention characteristic is due to the uniquestructure and electrical properties of the CNTs. To simplifythe discussion, we only consider the situation of SWCNT,since the multiwall CNTs are more complicated. As weknow, the structure of SWCNTs is one dimensional and thecharge carriers in the SWCNTs can only transport along itsaxis direction.21,22 Consequently the transport of charge car-riers along other directions will be strongly confined. There-fore the charges trapped in the SWCNTs may be difficult totunnel out. Another important reason may be the nearly per-fect surface quality of SWCNTs.22 Unlike Si and Ge nano-crystals, the SWCNTs have almost no dangling bonds ontheir surface corresponding to very few or zero surfacestates. According to the research results of Park et al.,24 thesurface states of the Si quantum dots play a very importantFIG. 4. Color online Charge retention characteristics of the CNT-basedMOS memory devices using ±5 V programming gate voltages.role in the charge loss of the memory devices. It has alsoaded 22 Aug 2011 to 158.132.161.52. Redistribution subject to AIP licbeen reported that the charge retention characteristics of theflash memory structures using Si, Ge nanocrystals as floatinggate are affected by many other mechanisms, such as thecharging characteristics electron or hole,25,26 interfacialstates between the Si substrate and tunneling oxide,27 defectsand surface states of the nanocrystals,24 size, shape, and ratioof volume to surface area of the nanocrystals,27,28 etc. Ac-cording to the research results in Refs. 25 and 26, memorydevices programmed by holes have better retention charac-teristics than that programmed by electrons due to theirhigher potential barrier and larger effective mass of holes.Similarly, excellent long term charge retention characteristicscan also be expected for the memory structures using CNTsas floating gate due to their hole trapping characteristics asdemonstrated in Fig. 3.This work is supported by Hong Kong CERG grantB-Q772 and the Center for Smart Materials, the Hong KongPolytechnic University 1-A324.1S. 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Memory effects of carbon nanotubes as charge storage nodes for floating gate memory applications

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