Jensen, Ole Kiel

Larsen, Torben

Mikkelsen, Jan H.

Shen, Ming

English

Compact modeling of P+ contact resistances is important for characterization of substrate noise coupling in mixed-signal System on Chips (SoCs). Existing contact resistance models can handle uniformly doped bulk or epitaxial substrates. However, compact contact resistance models feasible for modern lightly-doped CMOS processes with P-well layers are still unavailable. This paper presents a new compact resistance model aiming at solving this problem. A Conformal Mapping(CM) method was used to derive the closed-form expressions for the resistances in the model. The model requires no fitting factors, and it is scalable to layout/substrate parameters. The proposed model can also be used to predict noise coupling in terms of S-parameters. The model validation has been done by both EM simulations and measurements, and satisfactory agreement is found between the modeled and measured resistances as well as S-parameters

    Aalborg UniversitetA Compact P Contact Resistance Model for Characterization of Substrate Coupling inModern Lightly Doped CMOS ProcessesShen, Ming; Mikkelsen, Jan H.; Jensen, Ole Kiel; Larsen, TorbenPublished in:European Microwave Week 2012 Conference ProceedingsPublication date:2012Document VersionAccepted author manuscript, peer reviewed versionLink to publication from Aalborg UniversityCitation for published version (APA):Shen, M., Mikkelsen, J. H., Jensen, O. K., & Larsen, T. (2012). A Compact P Contact Resistance Model forCharacterization of Substrate Coupling in Modern Lightly Doped CMOS Processes. In European MicrowaveWeek 2012 Conference Proceedings EuMA.General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright ownersand it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.            ? Users may download and print one copy of any publication from the public portal for the purpose of private study or research.            ? You may not further distribute the material or use it for any profit-making activity or commercial gain            ? You may freely distribute the URL identifying the publication in the public portal ?Take down policyIf you believe that this document breaches copyright please contact us at vbn@aub.aau.dk providing details, and we will remove access tothe work immediately and investigate your claim.A Compact P+ Contact Resistance Model forCharacterization of Substrate Noise Coupling inModern Lightly Doped CMOS ProcessesMing Shen, Jan H. Mikkelsen, Ole K. Jensen and Torben LarsenDepartment of Electronic Systems, Aalborg University, Aalborg 9220, DenmarkAbstract—Compact modeling of P+ contact resistances isimportant for characterization of substrate noise coupling inmixed-signal System on Chips (SoCs). Existing contact resistancemodels can handle uniformly doped bulk or epitaxial substrates.However, compact contact resistance models feasible for modernlightly-doped CMOS processes with P-well layers are still unavail-able. This paper presents a new compact resistance model aimingat solving this problem. A Conformal Mapping(CM) method wasused to derive the closed-form expressions for the resistances inthe model. The model requires no fitting factors, and it is scalableto layout/substrate parameters. The proposed model can also beused to predict noise coupling in terms of S-parameters. Themodel validation has been done by both EM simulations andmeasurements, and satisfactory agreement is found between themodeled and measured resistances as well as S-parameters.I. INTRODUCTIONThe growing demand for powerful yet low cost electronicdevices has resulted in an increasing need for mixed-signalSystem-on-Chips (SoCs). SoCs require mixed integration ofboth digital circuits and analog/RF circuits on the same chip.However, the analog circuits in mixed-signal SoCs often sufferfrom substrate noise interference generated by the digitalcircuits [1]. Substrate noise coupling through P+ contacts isone of the three most significant noise coupling mechanismsleading to the interference [2], [3]. Fig. 1 illustrates thecoupling between P+ contacts located in digital and analogcircuits on a mixed-signal SoC. The switching noise generatedby the digital circuits is coupled through the P+ contact(Aggressor) into the P-well and substrate. This noise prop-agates to reach analog circuits sharing the same substrate,here represented as a P+ contact (Victim), and deteriorate thecircuit performance. Compared to other coupling mechanisms,including the source/drain-bulk junction capacitive couplingand impact ionization caused by hot electron effects, thecoupling effect of P+ contacts is much more significant forcurrent CMOS processes and is expected to remain so forfuture technologies [3], [4]. Various modeling approaches havebeen proposed and they can be categorized into two groups:electromagnetic methods and compact models [1], [3], [5]–[8].Compact models can provide the insights into the dependenceof the coupling on the layout/substrate parameters. Owingto its scalable feature compact models are efficient for largescale SoCs and consequently has attracted significant researchattention [1], [3], [8].(a)(b)t1t2RavaRasdavAggressorLaVictimLvAnalog/RF circuitsDigital circuitsMixed-signal SoCRvsSwitching noiseCoupledsubstrate noise P+ P+Ra Rva vP-SubstrateP-Well1, 12, 2Fig. 1. (a) Top-view and (b) cross section view of two P+ contactsimplemented using a modern lightly doped CMOS process with a P-welllayer. The proposed circuit model for the structure is also shown.Compact contact resistance models for substrate noise char-acterization were proposed as early as 1993 [1]. However theearly models are only feasible for epitaxial substrates. Anothermodel, proposed in 2006, is able to handle both epitaxialand uniform bulk substrates [3]. However, it requires threefitting factors that need to be extracted from measurements.Thus the noise analysis has to be postponed to the post-layout design stage, resulting in longer design cycle and highercosts. One of the latest compact contact resistance modelswas proposed in 2007 [8]. It needs no fitting factors andcan be used for both uniform bulk and epitaxial substrates.However, it is still infeasible for modern standard lightlydoped CMOS processes that are increasingly used for mixed-signal SoCs. Unlike uniform bulk or epitaxial substrates,lightly doped substrates of standard CMOS processes havea thin P-well layer on the P-substrate (Fig. 1(b)). The P-well layer introduces a current constriction effect which hassignificant impact on the coupling between the P+ contacts[9]. Existing compact contact resistance models do not includethe parameters of the P-well (ρ1, ￿1 and t1), and therefore cannot effectively characterize the coupling. To obtain accuratecoupling predictions and help the SoC designers solve theP-wellP-SubstrateP-Substrate(a)(b)P+contact P+contactP+contact P+contactFig. 2. The cross section view of the simulated currents between two P+contacts on (a) a typical lightly doped CMOS process with a P-well layer and(b) on a uniform bulk substrate. The parameters used for the simulation are:La = 20 µm, Lv = 20 µm, dav = 10 µm, t1 = 5 µm, t2 = 200 µm,ρ1 = 0.2 Ω−cm and ρ2 = 20 Ω−cm.noise issues, new contact resistance models feasible for lightlydoped substrates with a P-well layer are highly desired.This paper proposes a two-port resistive network as shownin Fig. 1(b) to model the resistance between the contacts.The constriction effects introduced by the P-well layer arecharacterized using a Conformal Mapping approach. Themodel is based on the investigation of the physical geometryof the contact layout, taking into account all the layout andsubstrate parameters shown in Fig. 1(b). Thus it requires nofitting factors.II. THE CONTACT RESISTANCE MODELThe proposed circuit model is shown in Fig. 1(b). Rava, Rasand Rvs represent the resistances between the dashed surfaces(Fig.1(b)). Ra and Rv model the current constriction effectsfor the aggressor and victim, respectively. The aggressor-victim contact resistance between port a and v, Rav , is dividedinto two parallel parts (Fig. 1(b)): the resistances in the P-welllayer (Ra, Rv and Rava) and the resistances in the P-substrate(Ras, Rvs). That is Rav = (Ra +Rava +Rv)||(Ras +Rvs).This is based on the fact that the resistivity of the P-well isusually one or two orders of magnitude lower than that ofthe P-substrate. Thus the majority of the noise current flowshorizontally from the aggressor to the victim in the P-well,while a small part of the current is coupled to the P-substrateat the area beneath the contacts. Fig. 2 illustrates the simulatedcurrent flows between two P+ contacts on a typical lightlydoped CMOS process with a P-well layer and on a uniformbulk substrate, respectively. It can be seen that the currentsin the case with P-well are remarkably constricted in the P-well layer, while the currents in the case without P-well arespreading in a much larger region in the P-substrate [10].To simplify the analysis, his paper approximates the layoutY·LzLzABC D EA` B`C`D`E`AB A` B`CD E E` D`C`Lz1z-planez1-planeX·LzWz1Conformal MappingFig. 3. Conformal mapping for the calculation of the constriction resistanceof a contact on a thin film.of the square contacts in Fig. 1 using circular contacts. Theapproximation is based on the condition that the circularcontacts have the same area as the corresponding squarecontacts. That is ra = La/√π and rv = Lv/√π, where raand rv are the radii of the circular contacts approximatingthe square aggressor and victim contact (with side lengthLa and Lv), respectively. The same approximation has beenwidely used in previous work, and it has been proven that theapproximation error is acceptable for practical use [8].A. Calculating Rava, Ra and RvBased on the contact approximation, the dashed blocks inthe P-well are approximated as two cylinders with radii of raand rv , respectively. As the relationship R = ρ1￿1/C standsfor homogeneous mediums, the resistance between the lateralsurfaces of the cylinders (Rava) can be easily derived fromthe capacitance between the surfaces [11]Rava =ρ12πt1acosh￿12￿D2rarv− rarv− rvra￿￿, (1)where D = dav + ra + rv . ρ1 and t1 are the resistivity andthickness of the P-well, respectively. It should be noted thatRava in (1) does not include the constriction resistances (Raand Rv) in the areas close to the contacts. In this paper, thiserror is corrected by equivalently extending the real distance(dav) with an equivalent distance Le for each of the contacts.This is achieved using a Conformal Mapping approach.The top figure in Fig. 3 shows the cross section viewof two identical co-planar contacts (C-D and C￿-D￿) on aconductive layer. Lz represents half of the distance betweenthe contacts plus the side length of the contacts. X and Yrepresent the ratio of the contact width and the thickness ofthe conductive layer. Simple expressions for the current flowlines (long dashed lines with arrows) and the equipotentialsurfaces (short dashed lines) at the constriction areas areusually unavailable in the original plane z [12], [13]. Hencethe resistance between the two contacts can not be easilyderived. However, using Conformal Mapping, the contacts inthe z-plane can be mapped to a new plane z1 (bottom figurein Fig. 3) with new distance Lz1 and contact width Wz1,where the structure is simple and the resistance can be easilyderived. Since the mapping is conformal, the current flows andequipotential surfaces are kept perpendicular to each other.This guarantees that the resistance value between the contactsin the z1-plane is the same as that in the z-plane. Thereforethe equivalent distance for constriction resistance correctionof the contact C-D can be easily found asLe = XLzLz1/Wz1 − (1− Y )Lz. (2)In the case of X << 1, and Y < 0.5, Le can be approximatedas [12], [13]Le ≈YX− 2πln￿sinh(Y π2X)￿, (3)and for the case of X << 1, and Y > 0.5, Le can beapproximated as [13]Le ≈K(p)/K ￿(p)− (1− Y )/X, (4)whereK is the complete elliptic integral of first kind and p =tanh[π(1− Y )/2X]. In addition, K ￿(k) = K(√1− k2).Using (1) and (3) or (4) the resistance between the contactsin the P-well (Ravw = Ra + Rv + Rava) in Fig. 1(b) can befound byRavw ≈ρ12πt1acosh￿12￿D21rarv− rarv− rvra￿￿, (5)where D1 = dav + Lea + Lev + ra + rv is the extendeddistance between the contacts. Lea and Lev are the equivalentdistances to correct the constriction resistances (Ra and Rv)for the aggressor and victim, respectively.B. Calculating Ras and RvsA typical P-substrate is usually two or three orders thickerthan the P-well . Thus the current in the P-substrate spreadsover a much larger region than the thin P-well (Fig. 2(a)). Thisleads to different calculations of Ras and Rvs compared to thecase of Rava. A simple expression of the contact spreadingresistance on a uniform bulk substrate has been reported in [8].It is used here to calculate the contact spreading resistancesin the P-substrate:Ras ≈ρ24ra￿1− 2πasin￿rara + dav￿￿. (6)Similarly, Rvs is formed using the same expression as (6)for Ras with ra replaced by rv .III. MODEL VALIDATIONA. EM simulation validationsThe proposed model has been validated firstly by EM sim-ulations using CST STUDIO SUITETM. The geometry in Fig.1 is used for the simulations and the modeled and simulatedresults for substrates with five different P-well resistivities(ranging from 0.01 Ω−cm to 0.2 Ω−cm) are shown in Fig. 4.!" ! "#$ $% $%%#$%!#&'"()*+',-.,/0)" 12%3%$2 45"" 12%3%62 45"" 12%3%72 45"" 12%3$2 45"" 12%362 45"$%%$%$$%6$%8Fig. 4. Modeled and EM-simulated contact resistance versus thickness ofthe P-well. The parameters used for the simulation are: La = 20 µm,Lv = 40 µm, dav = 20 µm, t2 = 200 µm and ρ2 = 20 Ω−cm.TABLE IPROCESS PARAMETERSt [µm] ￿/￿0 ρ [Ω-cm]P-Well 1.2 12 0.11P-Substrate 300 12 20It can be seen that the modeled resistances match the simulatedresults very well especially for small thicknesses. The relativeerror is < 5% when the thickness is less than 5 µm,which is the case for most currently available lightly dopedCMOS processes [9]. For relatively thicker P-wells, deviationsbetween the modeled and simulated results are observed. Thisis because the approximation of horizontal current flow in theP-well layer is less accurate for thick P-well layers. The resultsshown in the figure also indicate that this model can be usedfor a wide range of substrates with different resistivities.B. Experimental validationsTwo test chips fabricated using a standard 0.18 µm CMOSprocess were used to validate the proposed model. The processparameters are given in Table I. The microphotographs ofthe test chips for verification of contact resistances and noisecoupling in terms of S-parameters are shown in the embeddedfigures in Fig. 6 and Fig. 7, respectively. Pads on top metallayer are used for on-wafer resistance and S-parameter mea-surements. An example of the 3-D layout of the test fixture(cross section view) is shown in Fig. 5. The aggressor andvictim contacts are connected to the pads on the top metal layer(metal-6) using vias. As the resistivities of the vias and metalpads are remarkably lower than those of the P-well and P-substrate, their resistances are neglected in the measurements.The measured and calculated contact resistances versus dis-tance of P+ contact pairs with three different side lengths areshown in Fig. 6. It can be seen that the agreement between themodeled and the measured results is fairly good. The relativeestimation error is less than 6.5% for all the results. Fig. 7shows the measured and calculated |S21| between contact pairswith four different distances. As shown in the embedded figureTop metal PadViaP + contactTop metal PadP-WellP + contactViaP-SubstratedavFig. 5. The cross section view of an example layout showing the connectionof the P+ contacts to the measurement pads.! "! #! $! %! &! '! (! )! *! "!!!"# + ,-$"#+-"!!!#!!$!!%!!&!!'!!./0123/,/45.67/8% 9:#!: ,% 9:$!: ,%&9:%!: ,!"#$ % &"'$ % ('$ % !'$ % )'$ % *'$ %! +$!'$ %! +$,'$ %!"+$)'$ %%"'&%#'&%#$%&Fig. 6. Measured and modeled resistances versus distance of P+contacts withdifferent side lengths. The embedded figure is the microphotograph of the testchip. The parameters of the CMOS process are: t1 = 1.2 µm, t2 = 300 µm,ρ1 = 0.11 Ω−cm and ρ2 = 20 Ω−cm.in Fig. 7, G-S-G pads are used for S-parameter measurements.The connection of the contacts to the top metal signal pads isthe same as shown in Fig. 5. The ground pads only consistof metal-6 and are connected using two 10-µm wide metal-6strip lines. Fig. 7 shows that the calculated results have quitegood agreement with the measured results. The predict errorof the coupling is within 5 dB for the results except for thecase of dav = 525 µm from 3 to 10 GHz. It should be notedthat the coupling for this case is very weak (-50 dB), and therelatively big error might be due to the lower measurementaccuracy for weak coupling signals.IV. CONCLUSIONA compact resistance model for P+ contacts is proposed inthis paper. The model can handle lightly doped substrates witha thin P-well layer, which are common in modern deep sub-micron CMOS processes for the implementations of mixed-signal SoCs. The model is scalable to layout/substrate param-eters, while requiring no fitting factors. Test chips fabricatedusing a standard 0.18 µm CMOS process have been usedfor experimental verifications. Measured results show that themodeled contact resistances are accurate with estimation errorsless than 6.5%. It has also been demonstrated that the noise|S21|[dB]-60-50-40-30-20-10Frequency  [GHz]10.10.01010dav = 75 mdav = 225 mdav = 375 mdav = 525 mMeasurementModelFig. 7. Measured and modeled |S21|s of P+contact pairs with differentdistances. The side lengths for the aggressor and victim are both 75 µm Theembedded figure shows the layout of the test chip.coupling of contacts in mixed-signal SoCs can be accuratelypredicted using this model. This can be useful to solve thesubstrate noise issues in the early SoC design stage and reducethe design cost.REFERENCES[1] D. Su, M. Loinaz, S. Masui, and B. Wooley, “Experimental Results andModeling Techniques for Substrate Noise in Mixed-Signal IntegratedCircuits,” IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420–430, Apr.1993.[2] C. Mohamed, B. Barelaud, and E. Ngoya, “Physical Analysis of Sub-strate Noise Coupling in Mixed Circuits in SoC Technology,” in Proc.European Microwave Integrated Circuits Conference (EuMIC), Paris,France, Sep. 2010, pp. 274 –277.[3] H. Lan, T. Chen, C. Chui, P. Nikaeen, J. Kim, and R. Dutton, “Syn-thesized Compact Models and Experimental Verifications for SubstrateNoise Coupling in Mixed-Signal ICs,” IEEE J. Solid-State Circuits,vol. 41, no. 8, pp. 1817–1829, Aug. 2006.[4] M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen,and H. De Man, “Impact of Technology Scaling on Substrate NoiseGeneration Mechanisms,” in Proc. IEEE Custom Integrated CircuitsConf. (CICC04), San Jose, CA, Oct. 2004, pp. 501 – 504.[5] N. Verghese and D. Allstot, “Computer-aided Design Considerations forMixed-Signal Coupling in RF Integrated Circuits,” IEEE J. Solid-StateCircuits, vol. 33, no. 3, pp. 314 –323, Mar. 1998.[6] R. Gharpurey and R. Meyer, “Modeling and Analysis of SubstrateCoupling in Integrated Circuits,” IEEE J. Solid-State Circuits, vol. 31,no. 3, pp. 344–353, Mar. 1996.[7] A. van Genderen, N. van der Meijs, and T. Smedes, “Fast Computationof Substrate Resistances in Large Circuits,” in Proc. European Designand Test Conference, Paris, France, Mar. 1996, pp. 560 –565.[8] S. Kristiansson, F. Ingvarson, and K. Jeppson, “Compact SpreadingResistance Model for Rectangular Contacts on Uniform and EpitaxialSubstrates,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2531–2536, Sep. 2007.[9] S. Hazenboom, T. Fiez, and K. Mayaram, “A Comparison of SubstrateNoise Coupling in Lightly and Heavily Doped CMOS Processes for 2.4-GHz LNAs,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 574 – 587,Mar. 2006.[10] G. Norberg, S. Dejanovic, and H. Hesselbom, “Contact Resistance ofThin Metal Film Contacts,” IEEE Trans. Compon. Packag. Technol.,vol. 29, no. 2, pp. 371 –378, Jun. 2006.[11] D. Cheng, “Field and Wave Electromagnetics,” 2nd ed. Prentice Hall,1989.[12] P. Hall, “Resistance Calculations for Thin Film Patterns,” Thin SolidFilms, vol. 1, no. 4, pp. 277–295, Jan. 1968.[13] ——, “Resistance Calculations for Thin Film Rectangles,” Thin SolidFilms, vol. 300, no. 1, pp. 256–264, May 1997.

A Compact P⁺ Contact Resistance Model for Characterization of Substrate Coupling in Modern Lightly Doped CMOS Processes

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A Compact P⁺ Contact Resistance Model for Characterization of Substrate Coupling in Modern Lightly Doped CMOS Processes

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