Blaabjerg, Frede

Chen, Zhe

Wang, Xiongfei

English

The virtual output impedance loop is known as an effective way to enhance the load sharing stability and quality of droop-controlled parallel inverters. This paper proposes an improved design of virtual output impedance loop for parallel three-phase voltage source inverters. In the approach, a virtual output impedance loop based on the decomposition of inverter output current is developed, where the positive- and negative-sequence virtual impedances are synthesized separately. Thus, the negative-sequence circulating current among the parallel inverters can be minimized by using a large negative-sequence virtual resistance even in the case of feeding a balanced three-phase load. Furthermore, to adapt to the variety of unbalanced loads, a dynamically-tuned negative-sequence resistance loop is designed, such that a good compromise between the quality of inverter output voltage and the performance of load sharing can be obtained. Finally, laboratory test results of two parallel three-phase voltage source inverters are shown to confirm the validity of the proposed method

An improved design of virtual output impedance loop for droop-controlled parallel three-phase Voltage Source Inverters

https://vbn.aau.dk/ws/files/170816816/ECCE_Final_Paper_II_Xiognfei_Wang_2.pdf

An improved design of virtual output impedance loop for droop-controlled parallel three-phase Voltage Source Inverters

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