Awan, Mehmood-Ur-Rehman

Koch, Peter

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Combined matched filter and arbitrary interpolator for symbol timing synchronization in SDR receivers

    Aalborg UniversitetCombined Matched Filter and Arbitrary Interpolator for Symbol Timing Synchronizationin SDR ReceiversAwan, Mehmood-Ur-Rehman; Koch, PeterPublished in:Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits andSystems, April 14-16, 2010 Vienna, AustriaDOI (link to publication from Publisher):10.1109/DDECS.2010.5491797Publication date:2010Document VersionAccepted author manuscript, peer reviewed versionLink to publication from Aalborg UniversityCitation for published version (APA):Awan, M-U-R., & Koch, P. (2010). Combined Matched Filter and Arbitrary Interpolator for Symbol TimingSynchronization in SDR Receivers. In Proceedings of the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems, April 14-16, 2010 Vienna, Austria (pp. 153). IEEE Press.https://doi.org/10.1109/DDECS.2010.5491797General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright ownersand it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.            ? Users may download and print one copy of any publication from the public portal for the purpose of private study or research.            ? You may not further distribute the material or use it for any profit-making activity or commercial gain            ? You may freely distribute the URL identifying the publication in the public portal ?Take down policyIf you believe that this document breaches copyright please contact us at vbn@aub.aau.dk providing details, and we will remove access tothe work immediately and investigate your claim.Combined Matched Filter and Arbitrary Interpolatorfor Symbol Timing Synchronization in SDRReceiversMehmood-ur-Rehman Awan, Peter KochCenter for Software Defined RadioDepartment of Electronic Systems, Aalborg University, DenmarkEmail: (mura, pk)@es.aau.dkAbstract—This paper describes a low complexity multi-ratesynchronizer that makes use of a polyphase filter bank tosimultaneously perform matched-filtering and arbitrary inter-polation for symbol timing synchronization in a sampled-datareceiver. Arbitrary Interpolation between available sample pointsis achieved by selecting the appropriate filter in the bank havingthe polyphase partitioned matched filter, which provides theoptimal sampling time. Two different structures are consideredwhich are modified to perform combined arbitrary resampling.The computational complexity is analyzed to have the resourceoptimal solution. Simulation results are analyzed and their re-source utilization for Virtex-5 FPGA implementation is presented.I. INTRODUCTIONSoftware Defined Radios (SDR) are highly configurablehardware platforms that provide the technology for realizingthe rapidly expanding future generation of digital wirelesscommunication infrastructure. Many sophisticated signalprocessing tasks are performed in a SDR, including advancedcompression algorithms, power control, channel estimation,equalization, forward error control and protocol management.In recent years, the FPGA technology has undergonerevolutionary changes which has enabled implementationof SDR systems ever further. The gate densities andclock speeds of recent FPGA generations provide thecommunication system architect with a highly configurablelogic fabric that can be used for realizing sophisticatedreal-time signal processing functions [1]. Amongst the morecomplex tasks performed in a high data rate wireless systemis synchronization. A large amount of time is spent executingthis task, and normally significant amount of hardware andsoftware in a SDR is dedicated to synchronization [2].Physical layer synchronization of symbol timing is requiredwhen samples of the received signal are misaligned with thedata symbols generated by the transmitter. Synchronizationcan be done by the use of polyphase filter banks which allowgreater flexibility and efficiency in the receiver by computingonly those multiplications necessary for matched filteringwhile simultaneously interpolating to achieve a sample pointsufficiently close to the optimum [3].The development of the polyphase filterbank and itsapplication to perform the interpolations required for symboltiming synchronization is presented in [4]. The authorsof [3] extended the work presented in [4] by adding anadditional control loop for carrier synchronization aftermatched filtering. In our work we combine the polyphasestructures for performing the arbitrary interpolation and thematched filtering to have a single structure for symbol timingsynchronization.II. SYMBOL TIMING RECOVERYThere exist two standard DSP approaches to obtain timingrecovery in modern QAM receivers [5]. The first approachuses a polyphase interpolator to calculate the samples at thedesired locations from the offset samples provided by the freerunning ADC. These position corrected samples are processedin the receiver matched filter whose output, through a detector,forms a timing error signal to guide the interpolating filterre-sampling process [5]. The second approach folds theFig. 1. Maximum Likelihood (ML) control of (a) Polyphase InterpolatingFilter and of (b) Polyphase Matched Filter [5].interpolation process into a polyphase matched filter. Theseparate paths of this polyphase filter represent a collectionof filters matched to different time offsets between inputsample positions and the output sample peak correlation valueposition. The timing recovery process simply has to determinewhich filter that matches the unknown time offset betweeninput and output samples. Either process uses a phase lockedloop (PLL) to direct the pointer to the appropriate phase legof the polyphase filter [5].Figure 1 presents the structure of the two timing recoveryschemes based on the Maximum Likelihood (ML) error termformed from two matched filters. Fig. 1a shows the controlof the polyphase interpolator while the Fig. 1b shows theProceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.April 14-16, 2010. Vienna, Austria. ISBN (print): 978-1-4244-6610-8/10 control of the matched filters. The loop in Fig. 1a exhibits alarger transport delay through the cascade of two filters thandoes the loop in Fig. 1b through the delay of a single filter.Due to the additional delay, the polyphase interpolating filtermust have a slower (or lower bandwidth) loop filter than doesthe polyphase matched filter [5].III. SYSTEM DESIGNAs a case study we will now investigate an SDR-baseddesign of a BGAN (Broadband Global Area Network) satellitereceiver as shown in Figure 2. The ADC data sampled at57.85 MHz is down-sampled to 723.125 kHz by a cascadedstructure of 16:1 and 5:1 re-samplers. It is further requiredto match the received signal with the transmitted pulse shapeusing matched filtering along with the timing recovery, thusdelivering the output at 151.2 k-symbols/sec. Now the twodifferent approaches for timing recovery, mentioned earlierare employed and compared in order to achieve an optimalsolution, in terms of computational complexity.Fig. 2. SDR design for a BGAN satellite receiver. Data is sampled at 57.85MHz and down-sampled to 723.125 kHz by a cascaded structure of 16:1 and5:1 re-samplers followed by arbitrary interpolator and match filter for symboltiming recovery.In the first approach having separate interpolation and matchfilter, the timing error signal guides the interpolation filterre-sampling operation to achieve the timing synchronization.According to the system requirements, a sample rate of723.125 kHz is converted to 151.2 kHz. The rate conversionfactor is M (number of polyphase partitions or phases) times723.125/151.2 = 4.782, which therefore requires an arbitraryinterpolator. The structural diagram for the first approach i.e.,separate polyphase interpolating filter as shown in Figure 1a,replaced with arbitrary interpolator is illustrated in Figure 3.Figure 3 shows a cascaded structure of arbitrary re-sampler [6] and matched filter. Arbitrary re-sampler is basedon linear interpolation to a position between available outputpoints in an M-path interpolator. Interpolation is achieved bypolyphase lowpass filter, and the polyphase derivative filteris used for local slope correction. The polyphase lowpassand the polyphase derivative filters’ coefficient pointer isaddressed by the integer part of the phase accumulator. Thephase accumulator is a modulo-M (number of polyphaseFig. 3. Cascaded structure of arbitrary re-sampler and matched filter withML control of polyphase interpolating filter.partitions or phases) addition of the fractional offset factord acc and the error signal error sig generated by theloop filter. The fractional part of the phase accumulator ismultiplied with the derivative filter’s output and added to thelowpass filter’s output for the slope correction.In this case, the matched filter operates at twice thesymbol rate i.e., 2×151.2 kHz = 302.4 kHz, but the loopfilter still operates at 1 sample per symbol. So the requiredfractional offset factor d acc for the arbitrary re-samplercomes out to be M times 723.125/(2×151.2) = M×2.39.The polyphase interpolator filter is designed at upsampledfrequency 16×723.125 kHz (having 16 phases or subfilters)with transition band of 100-200 kHz and 60 dB side lobeattenuation. The resulting 320 coefficients are partitionedinto M=16 polyphase sub-filters (phases) each having 20coefficients. The fractional offset factor d acc then becomes38.26. The matched filter is designed with a roll-off factor of0.25, filter length of ± 4 symbols, and operating at 2 samplesper symbol, which results in 33 coefficients.A computational complexity analysis is required and in thiswork we define the complexity in terms of multiplicationsper second, similar to the definition applied in [7]:Rm = N × fs (1)Rm is multiplications/sec, N is the number of non-zerocoefficients, and fs is the input sampling frequency.In multirate filters, Rm can be reduced by a sampling rateconversion factor. For polyphase decimator:RmDEC = (N × fsi)/MRmDEC = N × fso (2)Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.April 14-16, 2010. Vienna, Austria. ISBN (print): 978-1-4244-6610-8/10 where fsi/M = fso, fsi is sample rate at input, and fso issample rate at output of a polyphase filter.For polyphase interpolator:RmINT = (N × fso)/LRmINT = N × fsi (3)(where fso/L = fsi)The computational complexity for the arbitrary resamplerand the matched filter turns out to be 2×(96.77)x106and 2×(9.98)x106 multiplications per second (M-Mult/sec),respectively. The factor 2 accounts for the complex operations.In the second approach, the interpolation process is foldedinto the polyphase matched filter which is realized by filterbank index selection, and therefore the separate interpolatingfilter following the matched filter is not required. Differentloop control structures for this kind of design are possible.An M-stage polyphase filter bank with input data sampled atapproximately N samples/symbol can be used in a loop thatoperates at (a) MN samples/symbol, (b) N samples/symbol,or (c) 1 sample/symbol [4]. It has been investigated fromsimulations that these loop architectures work only if theinput data rate is some integer multiple of the desired outputdata rate, but not for the case involving arbitrary re-samplingoperation. So it requires some modifications to embed thearbitrary re-sampling process.In order to have the arbitrary re-sampling process embeddedin the combined interpolation and match filtering operation,the cascaded approach presented in Figure 3 is modified bythe following steps and the modified design is presented inFigure 4.1) Replace the arbitrary polyphase interpolator low-pass (and polyphase derivative) filters with polyphasematched (and polyphase derivative matched) filters.2) Discard the previous matched and derivative matchedfilters.3) Reconnect the timing error and loop blocks tothe polyphase matched and the polyphase derivativematched filters as they were connected before to thematched and derivative matched filters.Fig. 4. Combined structure of arbitrary re-sampler and matched filter withML control of polyphase matched filter.To our knowledge, this modified design has not been publishedpreviously, and therefore we consider the concept as a newand innovative idea. The matched filter is designed with thefollowing specifications; roll-off factor of 0.25 with filterlength of ±4 symbols, and the loop operates at 1 sample persymbol, which results in 624 coefficients. Upsample L anddownsample M factors are 16 and 76.52, respectively. Thecorresponding computational complexity becomes 2×(94.35)M-Mult/sec. Based on the complexity analysis for the twodesigns (interpolating filter design and the modified polyphasematched filter design) as shown in Table I, it can be concludedthat our modified polyphase matched filter design leads to areduced computational complexity by more than 10%. Besidesthat in the first design, loop exhibits a larger transport delaythrough the cascade of two filters than does the modifieddesign’s loop through the delay of a single filter.Computational Complexity (M-Mult/sec)Separate Arbitrary interpolation (Arbitrary Resampler) 2×96.77and Matched filtering (Matched Filter) 2×9.98Combined Arbitrary interpolation 2×94.35and Matched filteringTABLE IIV. SIMULATIONSClosed-loop simulations are performed for the modifiedpolyphase matched filter design in order to demonstrate thefeatures of polyphase filterbank for performing combinedarbitrary interpolation and matched filtering for timingsynchronization. It uses ML timing error detector which canbe easily incorporated into the polyphase filter bank [4].Simulated input test signal for the BGAN receiver is a4-QAM signal having one desired channel with no noise andinterference. The matched filter is designed at an up-sampledfrequency of 32×723.125 kHz (having 32 phases or subfilters)with a roll-off factor of 0.25 and filter length of ±4 symbols.The resulting 1248 coefficients are partitioned into M=32polyphase sub-filters (phases) each having 39 coefficients.The fractional offset factor d acc becomes 153.042. Theproportional Kp and integral Ki gain values are set to 1.6617and 0.0033 respectively. Data samples at 1 sample/symbol areprocessed by the polyphase matched filter and the polyphasederivative matched filter filterbanks. The product of the twofilterbank outputs form the timing error which is updatedonce per symbol. The timing error signal is filtered by aproportional-plus-integrator loop filter which is required for asecond-order loop to track out the symbol clock frequencyoffset [8]. The loop filter output together with fractional offsetis used to control the increment in the modulo-32 counter(NCO) which becomes constant when the loop has achievedlock.Figure 5 shows the simulation results as eye and constellationdiagrams, both plotted for 30 to 4000 and 3000 to 4000symbols. It is seen that the loop filter converges the signal toProceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.April 14-16, 2010. Vienna, Austria. ISBN (print): 978-1-4244-6610-8/10 the desired constellation. Figure 6 demonstrates the loop filterresponse and the incrementation of the timing accumulator.The loop filter’s response converges and the NCO control(timing accumulator) settles to a constant steady-state value(153 in this case).−1 −0.5 0 0.5 1−15−10−5051015Eye Diagram at Output of time aligned  Matched Filter: (30−4000) symbols−1 −0.5 0 0.5 1−10−50510Eye Diagram at Output of time aligned  Matched Filter: (3000−4000) symbols−4 −2 0 2 4−4−3−2−101234Constellation at Matched Filter−4 −2 0 2 4−4−3−2−101234Constellation at Matched FilterFig. 5. Eye and Constellation diagram for 30 to 4000 and 3000 to 4000symbols. The plots for 30 to 4000 symbols give a messy picture due to non-aligned symbols before the synchronization has achieved.0 500 1000 1500 2000 2500 3000 3500 4000−2−1012Loop Filter Output0 500 1000 1500 2000 2500 3000 3500 4000150151152153154155Increment of Timing AccumumulatorFig. 6. Loop filter output and timing increment of AccumulatorV. FPGA IMPLEMENTATIONThe design is implemented on a Virtex5-vsx50tff1136-3FPGA. Block RAMs are used for storing filter coefficientsand DPRAM (Dual Port RAM) is used for loading of the inputdata samples as a delayed line required for filtering operation.The device utilization summary is tabulated in Table II. Thedesign can operate at a maximum frequency of 380.625 MHz.Device Utilization (Virtex5-vsx50tff1136-3)Number of Slice Registers 520 out of 32640 (1%)Number of Slice LUTs 533 out of 32640 (1%)Number of Block RAM/FIFO 3 out of 132 (2%)Number of DSP48Es 6 out of 288 (2%)TABLE IIVI. CONCLUSIONSIn this paper a combined matched filter and arbitray inter-polator for symbol timing synchronization in SDR receiverswas presented. Two different structures were considered forthis task, which were next applied for SDR implementationof a BGAN satellite receiver. A structure with ML controlof polyphase matched filter was modified to embed arbitraryinterpolation, which in terms of computational complexityis more efficient than the cascaded structure of arbitraryinterpolator and matched filter. We find a 10% reduction.Simulations for the modified structure with the loop operatingat 1 sample/symbol were presented to illustrate the responseof loop filter and timing accumulator. The loop filter’s conver-gence and constant timing accumulator reliably indicate theachievement of symbol timing synchronization. The structurewas finally implemented on a Virtex-5 FPGA having deviceutilization of 1% and maximum operating clock speed of380MHz.ACKNOWLEDGMENTThe research described in this paper is carried out inCenter for Software Defined Radio at Aalborg Universitytogether with the industrial partner Thrane & Thrane A/S,Denmark. A special thanks goes to Jan Harding Thomsen andBo Dyssegard from Thrane & Thrane A/S for their valuablediscussions and suggestions throughout the system design.REFERENCES[1] Chris Dick, fred harris, Michael Rice,”Synchronization in Software Ra-dios - Carrier and Timing Recovery Using FPGAs”,in IEEE Symposiumon Field-Programmable Custom Computing Machines, 2000.[2] H. Meyr, M. Moeneclaey and S. A. Fechtal, ”Digital CommunicationReceivers”, John Wiley & Sons Inc., New York, 1998.[3] Joseph Gaeddert. et. al.,”Multi-rate Synchronization of Digital Receiversin Software-Defined Radios” in Proceeding of the SDR 07 TechnicalConference and Product Exposition, 2007.[4] F. J. Harris and M. Rice, ”Multirate Digital Filters for Symbol TimingSynchronization in Software Defined Radios”, IEEE Journal on SelectedAreas of Communications, vol. 19, no. 12, December 2001.[5] Chris Dick, Benjamin Egg, fred harris,”Architecture and Simulation ofTiming Synchronization Circuits for the FPGA Implementation of Nar-rowband Waveforms” in Proceeding of the SDR 06 Technical Conferenceand Product Exposition,2006.[6] Fredric J. Harris, Multirate Signal Processing for Communication Sys-tems, Prentice Hall, 2006.[7] Ljiljana Milic, Multirate Filtering for Digital Signal Processing: MatLabApplications, Information Science Reference (December 26, 2008) ISBN-13: 978-1605661780.[8] F. M. Gardner, ”Phaselock Techniques”, New York: Wiley, 1979.Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.April 14-16, 2010. Vienna, Austria. ISBN (print): 978-1-4244-6610-8/10 

Combined Matched Filter and Arbitrary Interpolator for Symbol Timing Synchronization in SDR Receivers

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Combined Matched Filter and Arbitrary Interpolator for Symbol Timing Synchronization in SDR Receivers

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