Chip level decision feedback equalizer for CDMA downlink channel

Abstract

In most commercial wideband code division multiple access (W-CDMA) systems, the transmitted signal in the downlink channel is spread by orthogonal codes to accommodate different users. However, frequency selective fading destroys the orthogonality and causes multiple access interference (MAI). The rake receiver has been proposed for a receiver in the downlink channel. Although providing reasonable performance due to path diversity, the rake receiver does not restore the orthogonality. As a result, the MAI is still present at the output of the rake receiver and CDMA system becomes an interference limited system. Thus, a better approach to provide MAI suppression shall be considered. The chip level linear equalizer followed by a despreader is an attractive alternative receiver to restore the orthogonality and to suppress the MAI. However, the performance of the chip level linear equalizer depends on the spectral characteristic of the channel and may not be satisfactory for some channels. To overcome this difficulty, the chip level decision feedback equalizer can be used. To improve the performance further, multiple-input multiple-output (MIMO) channels by using multiple antennas can also be employed. Recent research in information theory shows that multiple antennas can mitigate multipath fading in a wireless channel, increase the information capacity of wireless communication systems dramatically, and improve the reliability of the communications over wireless channel.In this thesis, the chip level decision feedback equalizer for CDMA downlink channel with multþle antennas is investigated. The work includes the design of the chip level decision feedback equalizer when the space time spreading scheme and the Alamouti scheme are employed at the transmitter. Theoretical and simulation results show significant performance gains compared to the rake receiver and the chip level linear equalizer.Thesis (M.Eng.Sc.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2004

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