Bouganis, CS

Cheung, PYK

Constantinides, GA

English

Spiral - Imperial College Digital Repository

A Novel 2D Filter Design MethodologyChristos-Savvas Bouganis, George A. Constantinides and Peter Y. K. CheungDepartment of Electrical and Electronic EngineeringImperial College LondonLondon, U.K.Email: christos-savvas.bouganis@imperial.ac.ukAbstract— In many image processing applications, fast con-volution of an image with a large 2D filter is required. FieldProgramable Gate Arrays (FPGAs) are often used to achievethis goal due to their fine grain parallelism and reconfigurability.However, the heterogeneous nature of modern reconfigurabledevices is not usually considered during design optimization. Thispaper proposes an algorithm that explores the implementationarchitecture of 2D filters, targeting the minimization of the re-quired area, by optimizing the usage of the different componentsin the heterogenous device. Experiments show that the proposedalgorithm can achieve on average 55% reduction in the requiredarea when compared to current techniques.I. INTRODUCTIONIn recent years, many image processing applications haveappeared in the literature that require the use of large 2Dfilters. Moderate size examples can be found in face detec-tion/recognition applications [1] where kernels with size of23 × 23 pixels are used, and some more extreme examplescan be found in medical imaging where applications requirekernels with size of up to 63×63 pixels [2]. At the same time,real-time implementation is often required, making the use ofhardware acceleration a necessity [3].FPGAs are often used to achieve this goal due to theirfine grain parallelism and reconfigurability. Modern FPGAsare heterogenous devices, often targeting the DSP community,and thus providing a mixture of resources that can be usedby DSP applications. The two main silicon cores that areusually included in the recent devices are embedded RAMs[4] and embedded multipliers [5]. The first one provides fastdistributed memory access, while the second one provides highspeed accurate multiplication.Current techniques for 2D filter optimization for a modernreconfigurable device, such as word-length optimization [6]and singular value decomposition [7], do not take into accountthe heterogeneity of the device. However, research concerningthe exploitation of heterogeneity for a particular applicationhas recently started to appear in the literature. In [8], theauthors propose an approach for exchanging embedded RAMsfor multipliers, whereas in [9] the authors propose an algo-rithm that identifies part of the circuit that can be implementedin embedded RAMs.In line with this direction, the proposed algorithm departsfrom the current methods of 2D filter implementation byproviding an approach that makes explicit use of the het-erogeneity of the device targeting to designs that use lessarea. Furthermore, it provides a framework which allows thedesigners to move their designs to different points in the threedimensional design space of embedded RAMs, embeddedmultipliers, and 4-input look-up tables (4-LUTs), keeping thearithmetic error in the filter approximation at the same level.II. RELATED WORKThe paper focuses on the case where designs with highthroughput are required, but design latency is of secondaryimportance. For this reason, only pipelined techniques forimplementation of a 2D convolution filter are considered. Acommon technique for implementation of such a filter on anFPGA is to use constant coefficient multipliers and a numberof embedded RAMs. The constant coefficient multipliers areoften implemented as shift/add combinations using 4-LUTsand, to further optimize the design, the coefficients are some-times transformed using canonic signed digit recoding, whichreduces the required logic [10].Another technique exploits potential separability of a 2Dfilter into two 1D filters by using the Singular Value Decom-position (SVD) [7] to express the original filter as a linearcombination of separable filters. Using this technique, theinitial filter can be implemented as a set of 1D filters wherehalf of them are applied to the rows of the image, and theother half to the columns. By decomposing the 2D filter, thenumber of necessary multiplications may be reduced, at theexpense of using more embedded RAMs. The number of levelsof decomposition that are required depends on the separabilityproperties of the filter and the arithmetic accuracy for storingintermediate results.In this paper, we propose a novel algorithm which optimizesa 2D convolution filter implementation in a heterogenousdevice, given a set of constraints regarding the number ofembedded multipliers and 4-LUTs. The algorithm estimatesan approximation of the original 2D filter which minimizesthe mean square error and at the same time meets the user’sconstraints on resource usage.Researchers have explored algorithms that minimize thearea cost of a filter by representing the coefficients using anappropriate number of bits such that the final error at theoutput of the filter is bounded by a user defined value [6].These methods perform an exploration of the design space ata lower level than the proposed approach, since they do notconsider altering the computational structure of the filter. Theproposed technique is thus complementary to these previousapproaches.5320-7803-8834-8/05/$20.00 ©2005 IEEE.1DFIR(u)1DFIR(v)11DFIR(u)1DFIR(v)22D FIRLine BufferLine BufferLine BufferRasterline InRasterline OutA1A2EFig. 1. Diagram of the decomposition with N = 2III. ALGORITHM DESCRIPTIONThe proposed algorithm takes as input the impulse responseof a 2D filter F with size m×m and a set of constraints forthe available embedded multipliers M and slices1. It producesas output an approximation of the filter which minimizes themean square error and at the same time meets the set ofconstraints. The main idea behind the algorithm is to explorethe separability of the input 2D filter and decompose it to aset of separable filters (Ai) and a non-separable one (E):F =N∑i=1Ai + E (1)A diagram of the decomposition is illustrated in Figure 1,where the number of decomposition levels is N = 2. Theseparability exploration of the filter is performed using thesingular value decomposition algorithm [7] which decomposesa matrix into a linear combination of the fewest possibleseparable matrices. The algorithm implements the first K =M−N2m  decomposition levels using embedded multipliers,while the remaining N − K stages are implemented usinga combination of embedded multipliers and slices. The non-separable filter component, E, is always implemented usingonly slices. Thus, the decomposition of the filter can be writtenas:F =K∑i=1Ai +N∑i=K+1Ai + E (2)For example, let us assume a filter F with size 23× 23, 100available multipliers and N = 3. The algorithm determinesK = 2 and decomposes F as follows. It implements themasks A1 and A2 using only multipliers. As these areseparable masks they need only 2×23 multipliers per level ofdecomposition for a total of 92. These are implemented usingthe embedded multipliers, while mask A3 is implementedusing a combination of the remaining multipliers and slices.Finally, the non-separable component E is implemented usingonly slices.1A slice is a term used by Xilinx, one of the two major FPGA manufactur-ers, to denote a combination of two 4-LUTs together with additional circuitryto support efficient arithmetic.The algorithm can be divided into three stages. The multi-plier allocation stage, the decomposition stage and the refine-ment stage. An overview of the algorithm is given in Figure2. Each stage is described in detail below.A. Multiplier allocation stageIn this stage, the algorithm determines the number of levelsof decomposition K that can be implemented using onlyembedded multipliers. The algorithm decomposes the inputfilter F using the SVD algorithm into a set of separable masksas:F = UΛVT=N∑i=1λiuiviT (3)where U and VT are orthogonal matrices and Λ is a diagonalmatrix containing the eigenvalues λi. The eigenvalues aresorted in descending order, thus λ1 ≥ λ2 ≥ ... ≥ λN . ui andvi correspond to the ith columns of the U and V matricesrespectively. The algorithm reserves the appropriate embeddedmultipliers for the multiplications by λi and implements thefirst K masks using the remaining embedded multipliers.In order to take into account the error inserted due toquantization, the algorithm updates the input filter F at eachlevel of the decomposition as:F← F− uqvqT (4)where uq and vq correspond to the quantized vector of coeffi-cients√λiui and√λivi respectively. The SVD decompositionis repeated to the updated filter F until the first K masksare estimated. In this way, the decomposition of each filterstage is optimized, given the quantization of the coefficientsfor the previous levels. The algorithm then proceeds to thedecomposition stage.B. Decomposition stageIn the decomposition stage the algorithm further decom-poses the remaining input filter into a set of separable masksand a non-separable mask using the SVD algorithm. The restof the available embedded multipliers are assigned to some ofthe coefficients, as described below, while the remaining coef-ficients are represented using only one non-zero signed digit,allowing the associated multiplications to be implemented costfree in bit parallel hardware.The algorithm first allocates the available embedded mul-tipliers to the coefficients of the vectors ui and vi by takinginto account the coefficients from all the remaining levelsof the decomposition. The actual allocation is performedonly for selected coefficients of the first level of the newdecomposition. The rest of the coefficients for that level arequantized as before. Due to the fact that the coefficients arequantized, the eigenvalue of that level of decomposition is thenre-evaluated to correct for the quantization effects. The new533λ is calculated using the following system of linear equations[11]:Fvi = λiuiFT ui = λivi (5)The filter F is updated using (4), which has been adaptedin order to accommodate the λ parameter, and the process isrepeated for the remaining separable decomposition levels.The final level, which is the non-separable mask E, isformed by the resulting filter F where all the coefficients arequantized as before. This mask is actually the error term ofthe initial input filter F and its approximation using a set ofseparable masks and fixed-point arithmetic.C. Refinement stageIn the refinement stage, the algorithm assigns extra bitsto the coefficients that have the largest error due to thequantization process, in order to minimize the error of theapproximation. The quantization is performed using canonicsigned digit representation [10]. The addition of extra bits isconstrained by the number of available slices.In the case where the algorithm selects to update a coeffi-cient that belongs to the stage J of the decomposition, thena new eigenvalue λJ is estimated according to (5) using thevalues already estimated for the rest of the coefficients, and thewhole algorithm is repeated starting from the decompositionstage for the next level of decomposition. This is required be-cause the slice allocation of the later stages of decompositionfor minimizing the error in the approximation, depends on thevalues of the previous levels. The algorithm terminates whenone of the constraints is violated. Figure 2 summarizes thesteps of the algorithm. The final approximation to F is givenby:F ≈N∑i=1Âi + Ê (6)where Âi and Ê are the quantized Ai and E respectively.IV. COST MODELThe presented algorithm explores the cost of a 2D filterdesign in the three dimensional space of embedded RAMs,embedded multipliers, and slices, while simultaneously min-imizing the error in the approximation of the original filter.The cost model for the embedded multipliers and embeddedRAMs is straightforward. For the number of slices for therequired multiplications and the adder-trees that are requiredby the design, an upper bound estimate is derived from thenumber of non-zero bits in the canonic signed digit encoding,since it provides a fast but a reliable estimate of the requirednumber of slices.V. PERFORMANCE EVALUATIONFor the evaluation of the proposed algorithm, we focus onthe ability of the algorithm to find a design that fits in a givenarea of the reconfigurable device. Such devices are manufac-tured by regular repetition of a silicon tile, thus the relationAlgorithm: Optimized 2D filter design for N levelsof decompositionSet Foriginal ← FCalculate levels with only multipliers K = M−N2m Multiplier allocation stageFOR j = 1 : KUsing SVD estimate: F =∑i λiuivTiQuantize uq =√λ1u1 and vTq =√λ1vT1Set Âj ← uqvTqUpdate F as: F← F− ÂjENDSet ds = K + 1Decomposition stageFOR j = ds : NUsing SVD estimate: F =∑i λiuivTiDetermine coeff. to allocate embedded mulsQuantize the coeff. of uq ← u1 and vq ← v1Estimate and quantize new λq ← λ1 using (5)Set Âj ← λquqvTqUpdate F as: F← F− ÂjENDQuantize the coefficients of F and set Ê← FIF constraints are violated THEN EXITRefinement stageFind the coefficient c that is not allocated to anembedded multiplier and has the largestapproximation errorAssign extra bit for its representationLet c belongs to the J th level of the decompositionIF J == N THEN update ÊELSE update ÂJIF constraints are violated THEN EXITIF J == N THENGOTO Refinement stageELSEEstimate F← Foriginal −∑Ji=1 ÂiSet ds = J + 1GOTO Decomposition stageFig. 2. Outline of the algorithmbetween the number of slices, the number of embedded RAMsand embedded multipliers gives an indication for the relativenumber of resources that are found in the device in an areaof a certain size. The device that is used for the evaluation ofthe algorithm is the XC2V8000 high-end FPGA from Xilinx.It contains 168 embedded 18× 18 multipliers, 168 embeddedRAMs and 46,592 slices. Since we are interested in finding adesign that fits in a given area of the device, the max operatoris used to map the cost from the three dimensional space ontoone dimension, i.e.Total cost = max(#RAMs168,#MULs168,#slices46592)5341 1.5 2 2.5 3 3.5 4 4.5 500.10.20.30.40.50.60.70.80.91EigenvalueDecomposition LevelMask AMask BFig. 3. Plot of the eigenvalues of the masks10−2010−1510−1010−5100020406080100120140Area usage of the device (%)Mean Square ErrorMask A (CSD)Mask A (Proposed method)Mask B (CSD)Mask B (Proposed method)Fig. 4. Area usage of the design versus achieved mean square errorFor comparison, we test the proposed algorithm against adirect implementation of the 2D filters using constant coeffi-cient multipliers. The comparative design is also optimized byusing canonic signed digit representation for the coefficients.The performance of the proposed algorithm depends on theseparability properties of the filter under investigation. Thus,two 2D filters of size 21×21 pixels with different separabilityproperties are considered in order to assess the performance ofthe algorithm. Figure 3 illustrates the separability propertiesof the two filters by plotting their first five eigenvalues as afunction of levels of decomposition. According to the figure,MaskA is less separable than MaskB. Figure 4 shows thetotal cost as a percentage of the area of the device, usingthe proposed method and the direct implementation usingcanonic signed representation, versus the minimum squareerror that can be achieved for the filter approximation. It canbe concluded that the proposed algorithm reduces the totalcost by between 34% and 70% (mean 55%). The proposedalgorithm has less effect on MaskA than on MaskB since theformer is less separable. However, an improvement between34% and 55% (mean 47%) is still obtained. Also, for theMaskB curve, clear jumps can be seen in the mean square errorwherever the algorithm has inserted an extra decompositionlevel. This is because its eigenvalues are reduced substantiallyfor up to the third level of the decomposition, whereas inthe case of MaskA they do not decrease as much after thefirst level. Moreover, the proposed algorithm was applied tooptimize the filters that are used in [3]. An improvementby a factor of 30% on average was obtained. In the worstcase, where the separability property of the mask is poor, thealgorithm will behave as well as the current techniques.VI. CONCLUSIONThis paper presents a novel 2D filter methodology forheterogenous devices. The main point of departure from thecurrent algorithms for efficient 2D filter implementation is thatit explores the computational structure of the filter accordingto the different types of available resources in the device.Experiments with filters with size up to 21 × 21 and vari-ous separability properties have been performed. The resultsindicate a reduction in the total cost by a factor between 34%and 70% (mean 55%). Future work will involve the use ofword-length optimization techniques [6] to further enhance theperformance of the algorithm.ACKNOWLEDGEMENTThis work was funded by the UK Research Council underthe Basic Technology Research Programme “Reverse Engi-neering Human Visual Processes” GR/R87642/02.REFERENCES[1] S. Gong, S. McKenna, and A. Psarrou, Dynamic Vision: From Imagesto Face Recognition, 1st ed. Imperial College Press, 2000.[2] (2004) The xilinx website. [Online]. Available:http://direct.xilinx.com/bvdocs/appnotes/xapp241.pdf[3] C.-S. Bouganis, P. Y. K. Cheung, J. Ng, and A. A. Bharath, “A SteerableComplex Wavelet Construction and its Implementation on FPGA,” Field-Programmable Logic and its applications, September 2004.[4] S. Wilton, J. Rose, and Z. Vranesic, “The Memory/Logic Interface inFPGA’s with Large Embedded Memory Arrays,” IEEE Transactions onVery-Large Scale Integration Systems, vol. 7, no. 1, March 1999.[5] S. Haynes and P.Y.K.Cheung, “Configurable multiplier blocks for em-bedding in FPGAs,” Electronics Letters, vol. 34, no. 7, pp. 638–639,1998.[6] G. A. Constantinides, P. Y. K. Cheung, and W. Luk, “WordlengthOptimization for Linear Digital Signal Processing,” IEEE Transactionson Computer-Aided Design of Integrated Circuits and Systems, vol. 22,no. 10, October 2003.[7] W. Press, S. Teukolsky, W. Vetterling, and B. Flannery, NumericalRecipes in C. Cambridge University Press, 1992.[8] G. Morris, G. A. Constantinides, and P. Y. K. Cheung, “MigratingFunctionality from ROMs to Embedded Multipliers,” IEEE InternationalSymposium on Field-Programmable Custom Computing Machines, 2004.[9] S. Wilton, “SMAP: Heterogeneous Technology Mapping for AreaReduction in FPGAs with Embedded Memory Arrays,” ACM/SIGDAInternational Symposium on Field-Programmable Gate Arrays, February1998.[10] I. Koren, Computer Arithmetic Algorithms, 2nd ed. New Jersey:Prentice-Hall Inc., 2002.[11] G. Strang, Introduction to Linear Algebra, 3rd ed. Wellesley-CambridgePress, 1998.535

A novel 2D filter design methodology

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A novel 2D filter design methodology

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