Constandinou, T G

Georgiou, J

Toumazou, C

Spiral - Imperial College Digital Repository

An Auto-input-offset Removing Floating Gate Pseudo-differential Transconductor Timothy G Constandinou', Julius Georgiou'. and Chris Toumazou' I EEE Dept, Imperial College of Science, Technology and Medicine, London SW7 2BT, United Kingdom. Toumaz Technology Limited, Culham Science Centre, Abingdon, Oxfordshire, OX14 3DB, United Kingdom. 'Bioengineering Dept, Imperial College of Science, Technology and Medicine, London SW7 2BT, United Kingdom. 2 ABSTRACT Vdd Vdd Vdd A floating-gate pseudo-differential transconductor is presented, in which the differential input signal is allowed to have a dc offset. Normally such an offset would render a normal CMOS differential pair useless. The circuit "VX v y "  inherently removes any dc offset from the floating gates lout(-)  lO"I(+) by feedback mechanisms involving Fowler-Nordheim electron tunneling and hot-electron injection. This technique can enable direct cascading of several cells without amplifying and accumulating offsets, or can be used to generate differential current mode signals from a single voltage source that has a dc offset, as with an electret microphone. ~ .......  :+. .., ,> .. 1. INTRODUCTION 'Designers of analog integrated circuits often find dealing with offsets challenging. The conventional approach of _ _  .. using large blocking. capacitors in conjunction with resistive elements is unfeasible for single-chip designs, as these require unrealistically large areas for large time constants. Other schemes include intricate feedback loops for compensating of the offsets or complex clocking schemes [I], periodically calculating and subtracting the offset. Floating gate transistors have a conducting gate encapsulated in a high quality insulator such as SO2.  Charge can be removed or added to the floating gate by three mechanisms - I )  Increasing electron energy by UV light, 2) Using Fowler-Nordheim tunnelling [5] and 3) Hot electron injection. The last two mechanisms can be used to adjust the charge on the gate dynamically [2] [3] [4]. NMOS device hot-electron injection 121 131 141 171: In this process electrons near the surface of a semiconductor acquire more than about 3.2 eV of energy, typically by being accelerated in an intense electric field, such as that produced in devices operated in the weak inversion region. 3.2eV are enough to surmount the silicodsilicon-dioxide harrier and so once in the silicon dioxide conduction band, an electric field applied across the oxide can carry these electrons to the floating gate. In order to make the. drain-gate electric field favour hot V Figure 1: The auto-input-offset removing floating gate pseudo-differential transconductor. The negative feedback is provided by the physical mechanisms of electron tunnelling and nFET hot-electron injection. electron injection, the threshold voltage of an NMOS transistor is raised, by increasing the doping of the substrate. This is achieved by violating design rules in a true twin-well process by placing a PTUB directly on a p- substrate and placing a normal NMOS device on this highly doped substrate. Altematively in a BiCMOS process the bipolar base dopant can he used to increase the substrate doping [4]. The hot electron injection gate current increases linearly with the source current, over the whole of the sub-threshold range, when Vdb and Vgb are held constant [6] and is exponentially dependent on the drain- source voltage. The current due to this mechanism can be modelled using the following form: (?I = Where I i ,  is the hot-electron injection current, I, is the device source current, Vdc is the drain-channel voltage and p, Vi.j are fit constants. 0-7803-7761-31031917.00 0 2 0 0 3  IEEE 1-169 Fowler Nordheim Tunnelling 151 171: The quantum mechanical nature of electrons i.e. the wave nature, allow an electron to have a finite probability of crossing what was once thought o f  as an impenetrable oxide barrier. The probability of crossing the oxide, and hence the effective current can be increased by increasing the electric field strength across the barrier. Hence, using a Fowler - Nordheim form the tunnelling current can be modelled using the following form: f a x 6 0  -~ (2) V,"" -vg Where I,",, is the tunnelling current, Io is the pre-exponential current, t, is the oxide thickness, E" is the electric field strength, V,,, is the tunnelling voltage and VQ is the floating-gate voltage. By taking advantage of these mechanisms the pseudo- differential floating-gate transconductor presented can be driven with differential signals with considerably large, slowly drifting, dc offsets. Figure 1 shows the auto-input-offset removing floating- gate pseudo-differential transconductor. I,," = Ioe 2. QUALITATIVE OPERATION The circuit consists of a pair of source connected floating- gate NMOS devices with a diode-connected FET (47) to provide the sinking current. The floating-gate devices have increased substrate doping to improve the hot electron injection efficiency. Each branches output currents are mirrored by the top-end current mirrors (Q3 - Q6). This basic cell may be used to make a number of different circuit elements i.e. an op-amp, a driver for current mode differential circuits, etc. The diode-connected FET serves two purposes. Firstly it provides the necessary feedback to realize a pseudo- differential behaviour between the two floating-gate devices. Secondly, it provides adequate compression at the common-source node to delay the hot-electron injection mechanism, hence increasing the settling time-constant. The drain currents and tunnelling voltages are set such that, at the circuit's steady state operating point, i.e. I ,  = I , ,  the electron tunnelling and hot-electron injection currents balance one another. The complimentary nature of these mechanisms provides the necessary negative feedback to restore the steady-state dc operating point if a disturbance occurs. In other words, if the floating gate voltage decreases, the electron tunnelling to increase. Likewise, if the floating gate voltage increases, the hot-electron injection current would be the dominant, causing the voltage to decrease. The auto-offset removal action occurs as follows: I .  A slowly changing differential signal will have the effect of changing one (or both) of the floating gate voltages. 2. The two drain currents will change in opposite directions, i.e. if I,  increases then I2 will decrease. This is due to the action of the shift in the common source voltage of the floating-gate pair. The devices source voltage will be changed; hence the gate-source and drain-source . voltages will also change. This will cause an imbalance between the electron tunnelling and hot-electron injection mechanisms. This imbalance will result in charge transfer; either to or from the floating gates, thus adjusting their voltages back to their quiescent steady-state values. Therefore, the two drain currents will also return to their quiescent operating points, despite the inputs having a dc offset or low frequency drift. 3. 4. 5. 3. QUANTITATIVE OPERATION DC Analysis: Under steady-state conditions, i.e. = the output currents are equal and therefore the floating-gate voltages must also be equal and constant. For this to occur the net charge on the floating-gates must remain unchanged, which implies the mechanisms of electron tunnelling and hot-electron injection balance one another. I,"" - I ,  = 0 I &  (3) (21 = o  '"A .~",,."..-"fi. - PIsoe Applying Kircboffs Current Law (KCL) at the floating- gate node forms the following relationship. Where Ci. is the input capacitance, Cfg, is the total floating- gate capacitance, Vrg is the floating-gate voltage, V,. is the input voltage, It"" is the tunnelling current and 1, is the bot-electron injection current. mechanism becomes more dominant, causing the voltage 1-170 On applying an input signal, the contribution of the electron tunnelling and hot-electron injection currents can be considered as negligible, yielding: This indicates that applying a relatively positive input voltage will cause an increase in the floating-gate voltage. Consequently the source voltage will also rise due to an increase in current in the diode connected FET. This will result in the following conditions: Reviewing the net gate current (current into the floating gate) gives the expression: Evaluating the above conditions (7) into this expression (8) yields: The imbalance due to these mechanisms will bring the floating-gate and source voltages back to their quiescent steady-state values at which the equilibrium will be restored. AC Analysis: For small signals the model shown in figure 2 can be used as an approximation to the floating-gate input devices. [4] Figure 2: The small signal model for an NMOS floating gate device. Analysis of this model yields the following small-signal voltage transfer function between the external input and the floating gate node: To solve (9), the following substitutions are made: k = (1 - r,grog,sgm)' and A' = 2MC,, which reduce it to: Evaluating this expression gives the high-pass 3dEl roll-off at: f = 21mHz. This value is consistent with the simulation results shown in figure 5 .  4. SIMULATION RESULTS The following simulation results have been obtained by creating AHDL tunneling and hot-electron injection models adapted for this particular 0.8pm process from those extracted by Diorio et al. 121 [3] [4]. This auto-input offset removal mechanism is illustrated in figures 3 and 4. ,_." -.U-,*.,I S I S  , ,>-. 1 .,2,', I\, . , ~ ,  ,... -~--__.._-,,.*" I...... -. . ..-.... ..~.. I s, . m _ , I  i ,-.,- ~ ~ . .  ! L  ,%.\ 1.- ..-mi&*<...... ults for a dc step on t ,"̂  < _... 3." "<...,. /*" .%./"- Figure 3: Simul ) input. This illustrates the feedback mechanism by which the steady- state quiescent operating point is restored. The operation of devices Q1 and QZ are shown in the left and right plots respectively. In figure 3, a DC step is input to Wn(-) whilst Vin(+) is kept at a particular voltage. Consequently, an imbalance in the tunneling and hot-electron injection currents is shown 1-171 in the second row. This causes the disturbed floating-gate voltage to drift towards its original value, shown in the third row. Finally, the output currents follow the trend, shown in the bottom row. . _(.,., - -" - -, __.._~__._---A= L_-. \%W ... Figure 4 Simulation results for the auto-input-offset removing floating gate pseudo-differential transconductor to a voltage pulse superimposed onto a 3Hz sinewave. The results (from top to bottom) show: (i) input voltages, (ii) tunnelling and hot-electron injection currents, (iii) source and floating-gate voltage for device Q1 and (iv) output currents. 5. DISCUSSION This paper introduces the concept of the auto-input-offset removing floating gate pseudo-differential transconductor based on the mathematical equations that model its components. Its ability to remove any dc offset has been successfully demonstrated, through simulation. The system assumes matching of tunnelling and injection devices. As indicated by the work of Millard et al. [SI, the use of tunneling and hot-electron injection will deteriorate the matching. For demanding applications, some form of feedback to the individual tunneling voltages may be required. However as technologies scale, the required tunnelling voltages are reduced and the quality of the oxides become better allowing for greater matching. Also, as DiMaria et al. [9] have indicated, continual hot carrier injection and tunnelling will result in degradation of the oxide quality. Therefore when setting the tunnelling voltage (electric field strength) and floating-gate drain current (hot-electron energy,) they should be kept to a minimum in order to minimize oxide degradation effects. The use of a diode-connected device attached to the common-source node means that common-mode small signals are not rejected; however these may be removed by using a classical differential pair as  the next stage. Assuming a cascaded structure of independent amplifiers the offsets should have a zero mean and these are removed at every stage the resulting offset should he similar in magnitude to the individual devices. Future work can concentrate on using more advanced models in addition to dealing with practical issues such as layout and device matching. The circuits' sensitivity to process variation can he determined, which could result in models suitable for fabrication. /. l-.:lI*,,,c ,@,'. TrnnJtir r,,nll,ll .,.-A ,WA,. la", ,:A11 ,111 \ I /  J r * l  ( ,mi > Figure 5: Simulation results of ac analysis showing the high pass characteristic. The 3dB roll-off is at 24.1 mHz. 6. REFERENCES [ I ]  E. A. Vittoz, "Dynamic Analog Techniques", in Y .  Tsividis and P. Antognetti, "Design of MOS VLSI Circuits for Telecommunications", Prentice Hall, 1985. [2] P. Hasler, B. A. Minch, C .  Diorio and C .  Mead, "An Autozeroing Amplifier using pFET Hot-Electron Injection," in Proc. IEEE ISCAS 1996, Atlanta, CA, May 1996, Vol. 3, pp.325-328. [3] C. Diorio, "Neurally Inspired Silicon Learning: From Synapse Transistors to Learning Arrays", Ph.D. Thesis, Caltech, Pasadena, CA, May 1997. [4] P. Hasler, "Foundations of Learning in Analog VLSI," Ph.D. Thesis, Caltech, Pasadena, CA, 1997. [5] M. Lenzinger and E. H. Snow, "Fowler-Nordheim Tunnelling into Thermally Grown SiOz," J. Applied Physics, 1969, Vol. 40, pp. 278-282. [6] United States Patent No. 5,986,927, Minch, et al., November 16, 1999. [7] I. 1. Sanchez and T. A. DeMassa, "Review of carrier injection into the siliconisilicon-dioxide system," IEE proceedings - G ,  June 1991, Vol. 138, No. 3. [8] W. P. Millard, Z. K. Kalayjian and A. G. Andreou, "Calibration and Matching of Floating Gate Devices," in Proc. IEEE ISCAS 2000, Geneva, Switzerland, May 2000, Vol. 4, pp.389-392. [9] D. J. DiMaria, E. Cartier, D. Arnold, "Impact ionization, trap creation, degradation, and breakdown in silicon dioxide films on silicon," Journal of Applied Physics, April 1993, Vol. 73, pp. 3367-3384. 1-172 

An auto-input-offset removing floating gate pseudo-differential transconductor

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