Constandinou, TG

Georgiou, J

Toumazou, C

Electronics Letters

English

Spiral - Imperial College Digital Repository

A nano-power mixed-signal tuneable edge-detection circuit for pixel-level processing in next generation vision systems  T.G. Constandinou, J. Georgiou and C. Toumazou  Abstract: A useful nano-power circuit is presented for edge detection in integrated vision systems. Based on a compact front-end of only five MOS devices, this circuit features a tuneable threshold and discrete output; ideal for interfacing to digital electronics.   Introduction:  In next generation vision systems, the traditional software-based processing is being transferred to the front-end as custom in-built hardware. This provides the advantage of real-time operation; a necessity in many vision applications. This processing includes tasks such as edge detection [1], contrast enhancement and localised automatic gain control [2]. For these tasks to be realised in hardware; the circuits must fulfil three criteria; ultra-low power consumption, optimised circuit simplicity and robustness. These are all crucial for these circuits require to be implemented in every pixel.  In this letter a circuit block based on a differential pair is presented for the task of real-time edge detection. The circuit core is based on only five devices; all biased in weak inversion for nano-power operation. Furthermore, quantitative analysis of subthreshold matching confirms reliable and robust operation of this circuit block.  Circuit Description: The schematic shown in Fig. 1 illustrates two neighbouring pixels with interconnected edge detection circuitry. Included are the photodetector circuits (one required per pixel,) the edge detection circuit (shaded in grey,) and the bias current generator and copying circuits.  Devices D1, Q1 and D2, Q2 form the continuous-time logarithmic photodetector circuits for the two neighbouring pixels. The photocurrents I1 and I2 develop logarithmically related voltages (V1 and V2) across the diode-connected devices (Q1 and Q2 respectively.) This differential voltage (V1, V2) is connected to the PMOS differential pair (Q5 and Q6) sourced by the current I4 (mirrored from the bias current; Ibias.) The differential pair tail currents are sunk via the current mirror (Q7, Q8 and Q9) which is controlled by the tuning current; Itune.   The operation is as follows:  • Ibias is chosen to be the same order of magnitude as the minimum value of photocurrents I1 and I2 in order to ensure devices Q4, Q5 and Q6 are in saturation and operating in weak inversion.  • Itune is adjusted to lie in between Ibias/2 and Ibias and sets the allowed tolerance before indicating an edge and flagging it up. This will set the gate-source voltages of devices Q8 and Q9. This voltage will in turn determine the maximum current that can be sunk from the drains of Q8 and Q9 (Id8max and Id9max respectively). Assuming devices Q5 and Q6 are ideally matched, this circuit operates in one of two states:  1. V1=V2: Since Ibias/2 < Itune < Ibias then I5 < Id8max causing device Q8 to be in the ohmic region. This in turn will cause V5 to sit barely above ground and similarly Q9, I6 and V6 will behave in the same way. As a result of V5 and V6 both being low, Vout will also output low indicating there is no edge.  2. V1≠V2: For example, if V1 < V2 such that I5=Id8max then device Q8 is in saturation and V5 rises to just below Vdd. However I6<Id9max so device Q9 is still in the ohmic region, keeping V6 low. This will result in Vout outputting high indicating there is an edge.  Circuit Analysis: A general expression describing the basic operation of the MOS transistor in the weak inversion region is:  ⎟⎟⎠⎞⎜⎜⎝⎛⎟⎟⎠⎞⎜⎜⎝⎛−−⎟⎟⎠⎞⎜⎜⎝⎛−⎟⎟⎠⎞⎜⎜⎝⎛−⋅=TDTSTGD nVVnVVnVVII expexpexp0  (1)  Assuming devices Q5 and Q6 are operating in saturation, the following expression can be derived, expressing the output current (differential.)  ⎟⎟⎠⎞⎜⎜⎝⎛ −⋅=−Tbias nVVVIII2tanh 2165  (2)  This can be split as to provide the single-ended tail current expressions.  ⎥⎦⎤⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛ −+=Tbias nVVVII 215 tanh121 (3)  ⎥⎦⎤⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛ −−=Tbias nVVVII 216 tanh121 (4)  From (2,) the large and small signal transconductance of the differential pair can be derived [3].  ( )( ) ⎟⎟⎠⎞⎜⎜⎝⎛ −=−−=TTbiasm nVVVnVIVVdIIdG2sec22122165 , Tbiasm nVIg2=  (5, 6)  Expression (5) can be used to express the range of values for which the circuit will flag an edge detected.  ( )( ) 021 <−+− VVVGI ERRmtune   (7)  Where VERR is the error term expressing the total mismatch error in the differential pair as an input referred voltage.  Matching: An instrumental design issue for ensuring circuits operating in weak inversion will work is device matching. The device mismatch arises from process parameter variations mainly in gate oxide thickness and doping concentrations, resulting in device threshold voltage and drain current variations. Since the gm/I ratio is at a maximum for devices operating in weak inversion, this signifies that subthreshold circuits are those most affected by device mismatch [4]. Therefore for robust high performance circuits with good manufacturing yields; the micropower designer must not rely on absolute model parameters but rather on good matching between identically designed and carefully laid out devices. For example, in device pairs closely separated, the threshold voltage mismatch dependence on the active area is given by the following expression:  ovtth CLWAV +×=Δσ  (8) Where: σΔVth is the standard deviation in threshold voltage, W x L is the device active area and Avt and Co are fit constants. Simulating using a threshold voltage spread of (Vth±2σΔVth) covers 96% of mismatch deviations and therefore gives a good indication of mismatch related performance variations in addition to circuit robustness.  Simulations: This circuit was simulated using the Spectre simulator under the Cadence IC design environment with foundry supplied models for a standard 0.18um CMOS process. Figure 2 illustrates the tunability of this circuit, i.e. for different values of Itune, by plotting the output voltage (Vout) versus the differential input voltage (V1-V2.) Since V1 and V2 are logarithmic compressions of photocurrents I1 and I2, the differential input voltage (V1-V2) represents the ratio of the photocurrents (I1/I2.)  The device pairs (or groups) requiring to be well-matched in the presented circuit are listed in Table 1, including simulated results for different device sizes and their corresponding mismatch errors.  Conclusion: Presented is an elegant circuit cell for implementing a core processing task; edge detection in early vision systems. This technique not only offers a reduced circuit complexity to alternative methods but also the versatility of being able to dynamically tune the sensitivity. Using careful layout techniques, device mismatch has been kept to the critical minimum to guarantee both robustness and high manufacturing yield. As edge-detection is a fuzzy computation, for example this is to be used to determine boundaries of biological cells [5]; any mismatch will usually translate to a shifting of the edge by a pixel or two. Most importantly, having been designed to operate from a 1.8v supply requiring only 7nA current, the total power consumption per block is under 13 nano-watts!   Acknowledgements:  The authors wish to acknowledge the Basic Technology grant (UKRC GR/R87642/02) and the AMx technology grant (EPSRC GR/R96583/01,) in addition to Toumaz Technology Limited for sponsoring this research.  References: 1 ROWLEY, M.D., HARRIS, J.G., ‘A comparison of three one-dimensional edge detection architectures for analog VLSI vision systems,’ IEEE ISCAS, 1997, 3, pp. 1840-1843. 2 DELBRUCK, T., MEAD, C.A., ‘Analog VLSI adaptive logarithmic wide-dynamic-range photoreceptor,’ IEEE ISCAS, 1994, pp. 339-342. 3 GEORGIOU, J, ‘Micropower Electronics for Neural Prosthetics,’ PhD Thesis, 2002, Imperial College London, UK 4 PAPASOVIC, A, ANDREOU, A.G., WESTGATE, C.R., ‘Characterisation of Subthreshold MOS Mismatch in Transistors for VLSI Systems,’ Analog IC’s & Signal Proc., 1994, 6, pp. 75-85 5 CONSTANDINOU, T.G., LANDE, T.S., TOUMAZOU, C, ‘Bio-pulsating architecture for object-based processing in next generation vision systems,’ Electron. Letters, 2003, 39, (16,) pp. 1169-1170  Authors’ affiliations:  T.G. Constandinou, J. Georgiou and C. Toumazou (Imperial College of Science, Technology and Medicine, Exhibition Road, London, SW7 2BT, United Kingdom) E-mail: t.constandinou@imperial.ac.uk J. Georgiou and C. Toumazou: Also with Toumaz Technology Limited, Culham Science Centre, Abingdon, Oxfordshire, OX14 3DB, United Kingdom Figure Captions:  Fig. 1 Circuit schematic of the micropower discrete edge detector; the shaded area representing the devices repeated per edge detection element.  Fig. 2 Simulation results of output voltage (Vout) plotted against input differential voltage (V1-V2) for different values of Itune; illustrating the tuneable sensitivity. Assuming perfectly matched devices with Ibias=5nA.  Table Captions: Table 1 Simulation data for critically matched device groups with corresponding mismatch errors for various sizes; providing both local and output referred error. Assuming devices are of equal areas with Ibias=5nA and Itune=3nA. The shaded entries represent the selected device dimensions to be used.  Figure 1: Q1 Q3 Q4Q5 Q6Q7 Q9Q8Q2D1 D2X1IbiasItuneV1V3V4V5V6V2V7I1 I2I4I5 I6VoutVdd Vdd Vdd VddVdd Figure 2:  Table 1: Device Pair [Separation] W/L 2σΔVth  (mV) Local error (%Current) Input referred error (σΔVin/mV) Effect of mismatch Q1, Q2 [S=100µm] 3/3 2.462 6.80 1.055 Fixed pattern noise (FPN) will cascade to other blocks. 5/5 1.456 4.41 0.625 10/10 0.700 2.30 0.301 Q3, Q4 [S=10µm] 3/3 1.904 5.67 3.960 Variation in tunability amongst identical blocks. 5/5 1.298 4.76 3.010 10/10 0.842 3.85 1.706 Q5, Q6 [S=10µm] 3/3 1.904 1.77 0.816 Asymmetric operation, i.e. non-linear distortion. 5/5 1.298 1.66 0.557 10/10 0.842 0.77 0.361 Q7, Q8, Q9 [S=10µm] 3/3 2.830 9.09 3.894 Variation in tunability amongst identical blocks. 5/5 1.780 5.26 2.029 10/10 1.026 2.74 0.978   

A comparison of three one-dimensional edge detection architectures for analog VLSI vision systems,’

Analog VLSI adaptive logarithmic wide-dynamic-range photoreceptor,’

Bio-pulsating architecture for object-based processing in next generation vision systems,’ Electron. Letters,

Micropower Electronics for Neural Prosthetics,’

Nano-power mixed-signal tunable edge-detection circuit for pixel-level processing in next generation vision systems

Nano-power mixed-signal tunable edge-detection circuit for pixel-level processing in next generation vision systems

Abstract

Similar works

Full text

Available Versions

Spiral - Imperial College Digital Repository