Bauwelinck, Johan

BOSS, A

De Backer, Els

HORVATH, S

Mélange, Cedric

Qiu, Xing-Zhi

RAO, S

THORNTON, C

Vandewege, Jan

English

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Analog Front-End ASIC Requirements for a FDM Broadband Powerline System Enabling Co-Existence

Ghent University Academic Bibliography

Analog Front-End ASIC Requirements for a FDMBroadband Powerline System EnablingCo-ExistenceJ. Bauwelinck, E. De Backer, C. Me´lange, X.Z. Qiu, J. Vandewege∗C. Thornton, A. Boss, S. Horvath†, S. Rao‡∗Department of Information Technology, INTEC/IMEC, Ghent University41 Sint-Pietersnieuwstraat, 9000 Gent, Belgium†Advanced Communications Networks SA, ACN8A Rue Du Puits-Godet, 2000 Neuchatel, Switzerland‡Telscom A.G.20 Aarwilweg 20, 3074 Muri Bei Bern, SwitzerlandAbstract— This paper presents a feasible set of analog ASICrequirements optimized to achieve co-existence in a broadbandPower Line Communications (PLC) system based on FrequencyDivision Multiplexing (FDM). FDM is the most straightforwardway to achieve co-existence between different systems, however,this involves many design challenges at the circuit level. First,a short description will be given of the PLC system, which isunder development in the EU funded IST POWERNET project.It will be shown that conventional receiver architectures, typicallydesigned for Time Division Multiple Access (TDMA) schemes, arenot well suited for FDM systems e.g. due to challenges arisingfrom near/far situations. Solutions to improve the performancewill be discussed and simulation results will be presented ofthe proposed architecture, based on parameters extracted fromcircuit designs, to show the feasibility of high bit rates in FDMtransceivers.Keywords— Analog front-end, Co-existence, Frequency divisionmultiplexing, Peer-to-peer, Powerline communicationsI. INTRODUCTIONPOWERLINE communication systems are becoming moreand more widespread. Many different systems and stan-dards are developed, however, as more and more systemswill be deployed co-existence becomes increasingly important.This research is part of the EU funded IST POWERNETproject [1]. The goal of this project is to validate the “cognitivebroadband over powerline (CBPL)” technology in the field.The CBPL technology employs asynchronous, peer to peercommunications, instead of the commonly used master-slavecommunications, between the users in order to keep therequired transmit power spectral density as low as possibleto comply with the regulatory requirements [2]. The differentasynchronous channels are allocated in a flexible way toThe authors would like to thank the European Commission for supportingthe IST POWERNET project under the research contract 027953.Fig. 1. Peer-to-peer powerline system.Fig. 2. Spectrum containing several asynchronous channels.different frequency bands, the bandwidth of which dependson the service requirements.A. Peer-to-Peer Frequency Division MultiplexingFig. 1 together with Fig. 2 shows a peer-to-peer PLCnetwork in which different asynchronous channels are com-municating at the same time in different frequency bands. Inorder to achieve high data rates, through a higher number ofchannels, the system bandwidth is specified up to 60 MHzso that emerging multimedia services such as IPTV, HDTV,etc. can be supported. PLC systems face many challenges.This paper focuses on the analog front-end ASIC. It is clearthat the Analog Front-End (AFE) requires low noise andlow distortion; however, clear figures are often missing inpublications [3].B. Analog Front-End Design ChallengesFDM is often criticized because it would require morecomplex front-ends to address the near/far problem that wouldaffect the dynamic range [4]. On the other hand, FDM isundoubtedly the most straightforward way to achieve co-existence between PLC different systems, even HomeplugAV includes the possibility to use FDM for coexistence [4].However, if the system and the front-ends are not optimizedto support FDM, a significant performance penalty cannot beavoided. In a CBPL system, peer-to-peer communication isused, instead of master-slave communication. In this way, thedistance between the communicating nodes is reduced andthe transmit (TX) level can be lowered. As a consequence,the near/far problem is somewhat relaxed. On the other hand,FDM will always pose significant design challenges in theanalog front-end. This paper mainly focuses on the receiver(RX) part of the AFE, since this is the most critical part.Especially because it captures the complete used spectrumand the properties of the received signal spectrum depend onmany (poorly known) factors. The purpose of this paper is toshow the feasibility, of the ASIC integration of the AFE, basedon parameters extracted from ongoing circuit design of themost important building blocks. The remainder of this paperis organized as follows. Section II will show that conventionalAFE architectures, designed for TDMA schemes, are notreally suited to support FDM. Section III presents the designtrade-offs for an AFE architecture optimized to support FDM.Section IV presents simulation results, based on parametersextracted from circuit designs, to show the feasibility of theproposed AFE ASIC. Finally, conclusions are given in SectionV.II. CONVENTIONAL ANALOG FRONT-ENDSConventional PLC transceivers, such as described in[5][6][7][8][9], employ a straightforward architecture in theRX path mainly consisting of a low-noise amplifier (LNA),a low-pass filter (LPF), a variable gain amplifier (VGA) anda high speed analog-to-digital converter (ADC) as shown inFig. 3. This is a very good architecture for TDMA basedcommunication, in which the available bandwidth is assignedto a single user in a certain timeslot.However in a FDM system, the spectrum is shared bya number of users resulting in simultaneous communicationchannels, each having different properties. As a consequence,AD conversion of the entire band is not a robust solution inan FDM system for several reasons:1) A high number of bits (in fact signal-to-noise anddistortion ratio, SINAD) would be required for disad-vantageous cases:a) Only a small part of the spectrum (e.g. 1 to 16MHz out of 60 MHz) could be used so most of theAD dynamic range could be occupied by unwantedchannels.b) The power density of the wanted channel can besignificantly (e.g. 30 dB) weaker than the otherchannels.c) The peak-to-average ratio becomes worse: e.g. for20 channels using 128 carriers, the RX effectivelyreceives 2560 carriers.2) Higher bandwidths (e.g. 60 or even 100 MHz) areconsidered for next generation PLC systems, requiringadvanced AD converters (conversion rate e.g. 3 times thebandwidth (BW) depending on the analog anti-aliasingfilter), which cost tens of dollars. Moreover, at highconversion rates the signal-to-noise ratio (SNR) does notimprove as much as the number of bits ideally predict(e.g. the state-of-the art AD9461 130 Msps 16-bit ADCprovides 12.5 effective bits [10]).Fig. 3. Conventional AFE architecture.As a consequence, taking into account the powerline un-certainties and a FDM scheme, the requirements on ADconverters are huge if a minimum SNR is required in badconditions, especially for the next generation PLC systems upto 100 MHz (as considered in the IEEE P1901 working group).Another important aspect is that in an asynchronous peer-to-peer FDM system, channels can be added or removed fromthe spectrum at any time. This would require a more complexautomatic gain control (AGC), compared to the proposedarchitecture in Section III. Robustness against interferencesor blockers is one of the main advantages of the proposedFDM system, because signals in other frequency bands willbe filtered in the AFE.So in order to design a transceiver, optimized for a FDMsystem, we propose to use a frequency conversion schemein the analog domain so that analog filtering can be usedprior to AD conversion, thus relaxing the AD requirements.Moreover, making the on-chip filtering tunable (2 to 16 MHzin our proposed design) provides a flexible way to allocatea certain amount of bandwidth to specific users or services.Furthermore, the guard bands between channels can be maderelatively small by combining analog and very selective digitalfilters in the RX path. Another advantage is that our frequencyconversion based architecture (designed for up to 60 MHz)can be easily upgraded to higher frequencies (e.g. 100 MHzas considered in the IEEE P1901 working group) because theAD performance and implementation cost is not the limitingfactor in our architecture.III. PROPOSED ANALOG FRONT-ENDA. TransmitterThe discussion in Section II focused on the RX path becauseit is more critical than the TX path. However, the TX designis also critical in a FDM system. Care must be taken to limitspectral regrowth due to the non-linearity of the transmitter,especially of the line driver (because it handles the largestvoltage/current signals). These intermodulation (IM) productscould enter other (weak) channels. 30 dB notches as used inHomeplug AV at licensed frequency bands is not sufficient toprotect other frequency bands because the signal one wouldlike to receive could be attenuated by e.g. 40 dB. As thefrequency channel is not fixed, no fixed filter can be usedafter the line driver so that optimizing the linearity of the linedriver is very important, in combination with a predistortor inthe digital domain to pre-compensate the non-linear line drivercharacteristic. The trade-offs concerning TX architecture area bit different from the reasoning we did for the RX part.This is because digital-to-analog converters (DAC) with highconversion rate and high SINAD are commercially availableat relatively low cost or much easier to implement. Moreover,the TX has to process only one channel, in contrast to the RXsection. As a consequence, the TX path design can be based ona high-speed DAC, combined with digital mixers to upconvertthe baseband signal into a particular frequency band.B. ReceiverIn the RX path it is key to achieve a high dynamic range.First of all, the input referred noise should be below the noisefloor of the powerline system. Secondly, a high linearity isvery important to avoid that other frequency bands or blockersreduce the SINAD of the desired channel due to IM. Severaltechniques are considered to reduce the IM distortion. Thefirst priority should be to suppress undesired frequency bands,before the signal is amplified to a high swing. Up to the pointwhere the signal is filtered, the non-linearity should be suffi-ciently high. In case of a very strong input signal (compared tothe input-reffered 1 dB compression point), it is even desirableto attenuate the signal before mixing (trading of an increasedAFE noise floor against a reduction of the IM products). Afterfrequency conversion, fixed passive and/or active filters canattenuate the undesired channels before further amplificationtowards the ADC. In the following section it will be shownthat sufficient dynamic range and SINAD can be achieved ina frequency conversion RX based on an architectural modelusing parameters extracted from circuit level designs. This chipis under development and will be tested in the field in 2007.C. Receiver ModelA model was developed for the RX path to estimatethe SINAD in a realistic frequency conversion scheme. Forevery building block, the noise and 3rd order IM distortioncontribution is calculated depending on the gain, the input-referred noise and the 1dB compression point (CP) of theblock. Estimating the signal level is straightforward for everycarrier, the voltage at the output of stage i is given by:vout,i = α1,i vin,i (1)where vout,i is the output voltage, vin,i is the input voltageand α1,i is the voltage gain. The noise at the output of stagei is given by:vnout,i = AV√v2nout,i−1 + v2nin,i (2)where vnout,i is the rms output noise voltage of stage i,vnout,i−1 is the rms output noise voltage of the previous stage(i − 1) and vnin,i is the rms input referred noise voltagegenerated by stage i.Estimating the distortion due to 3rd order non-linearity (afully differential design is assumed) is more complex. Due tothe multicarrier modulation many terms should be taken intoaccount. The non-linear transfer characteristic of the stages isapproximated as:vout,i = α1,i vin,i + α3,i v3in,i (3)where α1,i is the voltage gain of stage i, and α3,i modelsthe 3rd order non-linearity of stage i. α3,i is related to the 1dB compression point (V1dB , in V):α3,i = (0.38)2α1,iV 21dB(4)The worst-case 3rd order IM product can be calculatedanalytically by:3 α3 v32N2(N2− 1)+ 14(N−(N mod 4−2)2− 1)2. . .+ 12(2N − 1) + 12(N2− 1). . .+ 14(N mod 4− 2)(N−(N mod 4−2)2− 1). . .+ N8(N2− 3)−14(N2− 3 + N mod 4−22)(5)where N is an even number of carriers, and v is theamplitude of each carrier. This formula was derived usingextensive enumeration of the 3rd order IM products. It is validfor the middle carriers, which experience more IM than thecarriers at the edges of the channel. No coding, or predistortionwas assumed to reduce the peak-to-average ratio. Based on thisIM level that each of the N carriers experiences, the 3rd orderdistortion after a certain block can be approximated as:IM3,i = α1,i IM3,i−1 + im3,1 (6)where im3,i is the 3rd order IM generated in stage i, IM3,iis the total IM at the output of stage i, which also includesthe (amplified) IM of the previous stage. Now that the IMdistortion is estimated at every carrier, the total IM distortioncan be calculated, and consequently also the SINAD.IV. SIMULATION RESULTSIn the receiver model, the gain of the different blocks canbe optimized automatically to maximize the SINAD. Since themaximum SINAD is a trade-off between noise and IM, thisis not a trivial job to do manually. Especially because the IMdepends on the signal level. The stronger the signal the higherthe SNR, but the lower the signal to distortion ratio. Fig. 4shows a simplified block diagram, corresponding parametersand a simulation result as an example.The parameters taken for the non-linearity and the noiseare derived from an ongoing circuit design. Several effects arenot included in this model e.g. phase noise, rejection of theimage frequencies due to the frequency conversion, rejectionof the aliasing frequencies due to the ADC, etc. because itwould make the simulation unnecessarily complex. Each ofthese factors can be kept well below the resulting SINADby a proper choice of the frequency conversion scheme, theAFE architecture and the circuit design. The details of theanalog design will be presented when measurement resultsbecome available; the purpose of this paper is to show thefeasibility and potential of an integrated frequency conversionfront end. Table 1 summarizes the simulation results as afunction of the attenuation between the TX and the RX takinginto account optimum gain settings at the different stagesand a BW of 1 MHz, a TX level of -60 dBm/Hz, 128carriers, and a powerline noise floor of -140 dBm/Hz. Thesimulation model also learns what range of gain settings isrequired at every step. This SINAD computer simulation didnot include interferences, however, this architecture is morerobust against the conventional architectures. The effect ofpeak-to-average-power ratio (PAPR) reduction techniques wasnot yet taken into account. Moreover, the 3rd order polynomialapproximation based on the 1 dB compression point oftenFig. 4. Simplified receiver block diagram including main parameters. Asimulation result shows the signal level, the noise and the 3rd order IM at theoutput of the different stages.Attenuation [dB] SINAD [dB] Modulation scheme0-40 >34 1024 QAM41-49 >28 256 QAM50-55 >23 64 QAM56-61 >17 16 QAM62-68 >10 4 QAMFig. 5. Summary of the applicable modulation schemeoverestimates the distortion for signals well below the 1dBcompression point because the 1 dB compression point isoften determined by clipping. Below the clipping point theIM is better compared to what is predicted based on the 1 dBcompression point.Several conclusions can be drawn from the results presentedin Fig. 5. First of all, sufficient SINAD can be achievedover a wide attenuation range. This enables high aggregatedata rates in a system optimized for FDM. Secondly, peer-to-peer operation can effectively increase the throughput inthe system. Assume for example the attenuation between twonodes is 70 dB, and that an intermediate node is available.The communication to the intermediate node can ideally usea modulation scheme of 1024 QAM.V. CONCLUSIONAn analog front-end ASIC, based on a frequency conversionarchitecture, has been proposed. It is shown that such schemesovercome the disadvantages of conventional architectures inPLC systems based on FDM enabling co-existence. A model ispresented to estimate the SINAD in a multi-carrier modulationscheme. Simulation results, based on parameters extractedfrom integrated circuits in development, show that high ag-gregate data rates can be achieved over a wide range ofattenuation.REFERENCES[1] IST POWERNET project presentation,http://www.ist-powernet.org/deliverables/IST-2004-027953-WP1-D1.1-R03.ppt[2] S. Horvath, A. Jamin, “System and Method for Data Communication overPower Lines”, WO 2004/091113 A1[3] D. Gutierrez, L.M. Torres, F. Blasco, J. Carreras, J.C. Riveiro, “In-homePLC ready for triple play”, in Proceedings of the 9th International Sym-posium on Power Line Communications and Its Applications (ISPLC),April 2005, pp. 366- 370.[4] Intellon, “Homeplug AG Technology Overview”, 2005.[5] Maxim Integrated Products, “MAX2980 Powerline Communication Ana-log Front-End Transceiver Datasheet Rev. 0”, Jan. 2005.[6] Analog Devices, “AD9866 Broadband Modem Mixed-Signal Front EndDatasheet Rev. A”, Dec. 2004.[7] S. Gault, P. Ciblat and W. Hachem, “An OFDMA Based Modem forPowerLine Communications over the Low Voltage Distribution Network”,in Proceedings of the 9th International Symposium on Power LineCommunications and Its Applications (ISPLC), Apr. 2005, pp. 42 - 46.[8] I. Mehr, P. C. Maulik and D. Paterson, “A 12-bit Integrated Analog FrontEnd for Broadband Wireline Networks”, IEEE Journal of Solid StateCircuits, vol. 37, No. 3, March 2002,[9] A. Sanz, J.I. Garc Nicol and I. Urriza, “A broadband modem mixed-signal front end for Power Line Communications”, in Proceedings ofthe 6th International Symposium on Power Line Communications and ItsApplications (ISPLC), March 2002, pp. 302 - 306.[10] Analog Devices, “16-Bit, 130 MSPS IF Sampling ADC (AD9461datasheet)”, May 2006.

Analog front-end ASIC requirements for a FDM broadband powerline system enabling co-existence

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Analog front-end ASIC requirements for a FDM broadband powerline system enabling co-existence

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