Bogaerts, Wim

Dumon, Pieter

Pathak, Shibnath

Van Thourhout, Dries

Vanslembrouck, Michaël

English

Ghent University Academic Bibliography

Effect of mask grid on SOIarrayed waveguide grating performanceS. Pathak∗, M.Vanslembrouck, P. Dumon, D. Van Thourhout and W. Bogaerts∗Photonics Research Group (INTEC), Ghent University - imec,Sint-Pietersnieuwstraat 41, B-9000 Ghent, BelgiumEmail: Shibnath.Pathak@intec.UGent.beAbstract—We studied the impact of the lithography mask gridon the performance of silicon AWGs, and show a dramaticimprovement in crosstalk of 5dB when going from a 5nm toa 1nm grid.I. INTRODUCTIONArrayed waveguide gratings (AWGs) are one of the commonlyused devices for wavelength multiplexing [1]. However, insilicon, AWGs have always lagged in performance comparedto the other techniques, such as silica [2] and InP [3]. Whilesilicon AWGs can be much smaller because of the highrefractive index contrast, the same high index contrast givesrise to phase errors and other parasitics which contributeto the overall crosstalk of the device. In general, siliconAWGs achieve crosstalk levels of -20dB, with the best devicesshowing -25dB crosstalk [4]–[6].II. PHASE ERRORSThe key contributor to crosstalk in silicon AWGs is thephase errors that are accumulated along the delay lines. Whenthe distributed light in the waveguides recombines in the freepropagation region (FPR), phase errors will translate in ripplesin the optical phase front. These ripples will induce sidelobesand overall crosstalk in the image at the output waveguides,resulting in optical power coupled to the wrong outputs. Wecan distinguish these phase errors in the delay lines into twocategories: deterministic and stochastic errors. In the lattercategory we find sidewall roughness and line-width/thicknessvariations as key causes. Using wider waveguides in the delaysections can alleviate the impact of theses effects [4]–[7].For the deterministic errors, we studied the effect of maskdiscretization on the performance of the AWG.As the common design of our AWGs uses rectangularwaveguide layouts [4]–[6] where the bend sections are gener-ally identical between the delay lines, we first looked at theeffect of the mask grid on the straight delay sections of theAWG. The effect is illustrated in Fig. 2. The path for thedelay line is calculated along 3 sides of a rectangle (takinginto account the length of the bends). During that calculation,the coordinates of the sides are calculated to high precision.However, during subsequent tape-out to a GDSII mask file, thecoordinates are snapped to a fixed grid. In practice, we useda 5nm grid, which means the length deviations in each armcould be ±15nm, which translates in phase errors of ±pi/19.By going to a 1nm grid, these variations drop to ±3nm, orsourceCircularphasefrontCircularphasefrontCircularphasefrontsourceimagedistortedphasefrontimagecrosstalkprefectly controlled delaysall contibutions arrive in phasereal-life delay linesphase errors at the outputsFig. 1. Schematic diagram of the AWG with ideal delay lines and with phaseerror affected delay lines.phase errors of ±pi/96. While the grid snapping in our maskdesign is fairly random (a rounding error depending on thecalculated delay length), it is a deterministic process: twoidentically designed AWGs will experience the same phaseerror contributions from grid snapping.aa-a/2 -a/2-a/2-a/2-a/2-a/2mask grid widthwaveguide axisworst possible align of an waveguide axiswaveguide axis align on mask gridFig. 2. The length deviation of a waveguides due to the grid snapping.We studied the effect of phase errors through simulation andexperimentally, by designing and simulating a set of identicalAWGs on both a 1nm and a 5nm grid, and fabricated themside-by-side.Transmission in dB−120−100−80−60−40−200Wavelength in µm1.5437dB49dB1.55 1.56 1.57 1.58Without grid snapping 1nm grid snapping5nm grid snappingFig. 3. Simulated transmission spectrum of 16 × 400GHz AWG (8thchannel) for 1nm, 5nm and without grid snapping.TABLE ICOMPARISON OF MEASURED AWG INSERTION LOSS (IL, CENTERCHANNEL AND OUTER CHANNEL) AND CROSSTALK LEVEL BETWEEN 1NMAND 5NM MASK GRID DISCRETIZATION.Channels Spacing Area IL XT XT FSR5nm 1nm[GHz] [µm2 ] [dB] [dB] [dB] [nm]4 400 468 × 237 -1.8 -2.2 -22 -27 198 400 490 × 307 -1.3 -2.7 -21 -26 3216 400 530 × 435 -1.5 -3.5 -21 -26 54III. SIMULATIONThe AWGs are simulated by a semi-analytical model [5]integrated with our design software (IPKISS) [8]. As wewant to illustrate the effect on the crosstalk due to the phaseerrors introduced by the grid snapping we didn’t include anystochastic phase error due sidewall roughness.Fig. 3 shows the simulated spectral response of the 8thchannel of a 16 × 400GHz AWG without grid snapping,and for 1nm and 5nm snapping. The simulation indicates, asexpected, that the insertion loss will not be affected while thecrosstalk floor will increase with increasing grid snapping. Inthe simulation we can see that the crosstalk is improved by12dB as we change the grid from 5nm to 1nm.IV. EXPERIMENTWe also fabricated a set of identical AWG designs, but witha different mask discretization. Fig. 4 shows the measuredspectral response of a 16 × 400GHz AWG using 5nm and 1nmgrid snapping. We see that the crosstalk is substantially highercompare to the simulated AWGs, because other crosstalkmechanisms are still present. But we do see a significantimprovement for the 1nm mask grid: The crosstalk floordrops from -21dB for the 5nm grid to -26dB for the 1nmgrid, making this the best published device with such a highchannel count. Other AWGs, with different channel counts,show similar improvements, as listed in table I.1.51 1.52Transmission in dBWavelength in nm1.53 1.54 1.55 1.56 1.57-300-10-201.51 1.52 1.53 1.54 1.55 1.56 1.57-300-10-201nm grid snapping5nm grid snappingFig. 4. Experimental transmission spectrum of 16 × 400GHz AWG using5nm and 1nm grid snapping.V. CONCLUSIONWe demonstrate a significant improvement in silicon AWGsby going from a 5nm mask discretization to a 1nm mask grid.We see an experimental improvement of 5dB in crosstalk dueto snapping-related phase errors. We illustrated this with a 16× 400GHz AWG with -26dB crosstalk level by reducing themask grid from 5nm to 1nm.ACKNOWLEDGMENTPart of this work was carried out in the framework ofIMEC’s Optical IO Industrial Affiliation Program.REFERENCES[1] C. Dragone, “An n×n optical multiplexer using a planar arrangement oftwo star couplers,” Photo. Tech. Lett., vol. 3, pp. 812–815, Sept 1991.[2] R. Adar, C. Henry, C. Dragone, R. Kistler, and M. Milbrodt, “Broad-bandarray multiplexers made with silica waveguides on silicon,” J. LightwaveTech., vol. 11, pp. 212 –219, Feb 1993.[3] H. Bissessur, F. Gaborit, B. Martin, P. Pagnod-Rossiaux, J.-L. Peyre, andM. Renaud, “16 channel phased array wavelength demultiplexer on inpwith low polarisation sensitivity,” Electron. Lett., vol. 30, pp. 336 –337,Feb 1994.[4] W. Bogaerts, S. Selvaraja, P. Dumon, J. Brouckaert, K. De Vos,D. Van Thourhout, and R. Baets, “Silicon-on-insulator spectral filtersfabricated with cmos technology,” J. Sel. Top. Quant. Electron., vol. 16,pp. 33 –44, Jan-Feb. 2010.[5] S. Pathak, M. Vanslembrouck, P. Dumon, D. V. Thourhout, and W. Bo-gaerts, “Optimized silicon awg with flattened spectral response using anmmi aperture,” J. Lightwave Tech., vol. 31, pp. 87–93, Jan 2013.[6] S. Pathak, M. Vanslembrouck, P. Dumon, D. V. Thourhout, andW. Bogaerts, “Compact soi-based polarization diversity wavelength de-multiplexer circuit using two symmetric awgs,” Opt. Express, vol. 20,pp. B493–B500, Dec 2012.[7] K. Sasaki, F. Ohno, A. Motegi, and T. Baba, “Arrayed waveguide gratingof 70x60 um2 size based on Si photonic wire waveguides,” Electrn. Lett.,vol. 41, no. 14, pp. 801–802, 2005.[8] W. Bogaerts, P. Dumon, E. Lambert, M. Fiers, S. Pathak, and A. Ribeiro,“Ipkiss: A parametric design and simulation framework for silicon pho-tonics,” in 9th IEEE Int. Conf. Group IV Photonics, pp. 30–32, Aug 2012.

Effect of mask grid SOI arrayed waveguide grating performance

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Effect of mask grid SOI arrayed waveguide grating performance

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