In this article, we present an efficient way of implementing 90 phase shifter using Hilbert transformer with canonic signed digit (CSD) coefficients in FPGA. It is implemented using 27-tap symmetric finite impulse response (FIR) filter. Representing the filter coefficients by CSD eliminates the need for multipliers and the filter is implemented using shifters and adders/subtractors. The simulated results for the frequency response of the Hilbert transformer with infinite precision coefficients and CSD coefficients agree with each other. The proposed architecture requires less hardware as one adder is saved for the realization of every negative coefficient compared to convectional CSD FIR filter implementation. Also, it offers a high accuracy of phase shift

Bauwelinck, Johan

Duraiswamy, Punithavathi

Vandewege, Jan

EURASIP Journal on Advances in Signal Processing

English

Punithavathi Duraiswamy

Johan Bauwelinck

Jan Vandewege

Springer - Publisher Connector

Efficient implementation of 90° phase shifter in FPGA

RESEARCH Open Access
Efficient implementation of 90° phase shifter
in FPGA
Punithavathi Duraiswamy*, Johan Bauwelinck and Jan Vandewege
Abstract
In this article, we present an efficient way of implementing 90° phase shifter using Hilbert transformer with canonic
signed digit (CSD) coefficients in FPGA. It is implemented using 27-tap symmetric finite impulse response (FIR)
filter. Representing the filter coefficients by CSD eliminates the need for multipliers and the filter is implemented
using shifters and adders/subtractors. The simulated results for the frequency response of the Hilbert transformer
with infinite precision coefficients and CSD coefficients agree with each other. The proposed architecture requires
less hardware as one adder is saved for the realization of every negative coefficient compared to convectional CSD
FIR filter implementation. Also, it offers a high accuracy of phase shift.
Introduction
Phase shifters have wide spread applications [1-3], in
particular, 90° phase shifters are used in wireless com-
munication for single side band generation, IQ modula-
tion and image rejection. Digital implementation of 90°
phase shifters is in high demand as many of the digital
communication systems use FPGAs [4-6]. The FPGAs
offer a wide range of performance for implementing
DSP algorithms and hence it is important to efficiently
map the algorithm in order to optimize the area and
speed. Hilbert transformer is the most widely used 90°
phase shifter implemented either by a finite impulse
response (FIR) [7-9] or by an infinite impulse response
(IIR) filter [10]. Since the Hilbert transformer is required
to shift the phase by 90° over a wide range of frequen-
cies, FIR filter with linear phase is preferred over IIR fil-
ter. The conventional method of implementing the FIR
filter is by adders/subtractors and multipliers. The com-
putational time of a multiplier is more than that of an
adder/subtractor and also occupies more hardware. In
order to increase the speed and reduce the hardware
cost, the coefficients of the filter are represented in
canonic signed digits (CSD), which is the representation
of the coefficients in powers of two. The resulting FIR
filter can be implemented using shifters and adders/sub-
tractors without multipliers. The CSD coefficients have
minimum number of non-zero values when compared
to other radix-2 representations which in turn again
reduces the number of adders [11]. In this article, an
efficient way of implementing the FIR filter with CSD
coefficients is proposed which reduces the number of
adders/subtractors compared to the convectional way of
implementing the filter with CSD coefficients. In our
application, this 90° phase shifter is used for digital
image rejection of a demodulated RF signal on the recei-
ver side of a wireless communication system.
CSD representation of filter coefficients
Encoding a binary number such that it contains the few-
est number of non-zero bits is called canonic signed
digit (CSD). It maps a number to a ternary system
{-1,0,1} versus a binary system {0,1}. The following are
the properties of CSD numbers:
No two consecutive bits in a CSD number are non-
zero.
The CSD representation of a number contains the
minimum possible number of non-zero bits, thus the
name canonic.
The CSD representation of a number is unique.
Among the N-bit CSD numbers in the range [-1,1], the
average number of non-zero bits is N/3 + 1/9 + O(2 -
N).
Hence, on average, CSD numbers contain about 33%
fewer non-zero bits than two’s complement numbers
[11]. Now the multipliers in the digital filters are rea-
lized using shifters and adders/subtractors. This results
in the area reduction for digital filters. Here, the
* Correspondence: punithavathi@intec.ugent.be
Ghent University, INTEC/IMEC, Sint-pietersnieuwstraat 41, 9000 Ghent,
Belgium
Duraiswamy et al. EURASIP Journal on Advances in Signal Processing 2011, 2011:32
http://asp.eurasipjournals.com/content/2011/1/32
© 2011 Duraiswamy et al; licensee Springer. This is an Open Access article distributed under the terms of the Creative Commons
Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in
any medium, provided the original work is properly cited.
complexity of a digital filter is a function of the number
of non-zero digits in the filter coefficient. Encoding the
filter coefficient using the CSD representation reduces
the number of partial products as well as the area and
the power consumption. Hence, it is a useful technique
for implementing FIR Filters with fixed coefficients.
Digital FIR filters can take advantage of this CSD
representation.
In order to simplify the hardware, the filter is designed
with coefficients represented by powers of two (CSD).
The following are the specifications used for the FIR fil-
ter design.
• Symmetry: Negative
• Sampling frequency: 140 MHz
• Pass band (normalized): 0.1-0.9
• Number of taps: 27
• Pass band ripple: 0.1 dB
• Stop band attenuation: 50 dB
• Coefficients precision: 12 bits
• CSD precision: 2
The following steps are followed for the design in
MATLAB:
(1) Determine the filter coefficients using Parks-
McClellan FIR filter.
(2) Convert the filter coefficients to finite precision
coefficients.
(3) Represent each coefficient in CSD using the algo-
rithm in [11].
The Parks-McClellan algorithm is optimal in min-max
sense, however, suffers from pass band ripples. For
applications that require zero ripple in the pass band
and small transition bandwidth, maximally flat FIR fil-
ters can be used which have zero ripple in the pass
band [12]. The coefficient precision can be varied till
the response is close to the infinite precision frequency
response. The number of taps as well as the digits in
the CSD is kept minimum for efficient hardware imple-
mentation. The number of taps is varied till the desired
response is obtained. The number of filter taps after
optimization is 27 and the CSD coefficient precision is
12 bits. Table 1 gives the CSD coefficients generated
from the algorithm in [11] from MATLAB. The fre-
quency response of the Hilbert transform with infinite
precision coefficients and CSD coefficients are shown in
Figure 1 and they agree with each other.
Hardware architecture
The proposed hardware architecture is shown in Figure
2. The architecture consists of two basic blocks: coeffi-
cient add/sub and tap adder. The delays are modeled as
Flip-Flop.
Direct Form II filter architecture is chosen for imple-
mentation. Negative powers of two is equivalent to divi-
sion by powers of two and can be implemented by
Table 1 CSD representation of filter coefficients.
Coefficient Value CSD representation
h(0) = -h(26) -0.00774850 -2-7 + 2-12
h(1) = -h(25) 0 0
h(2) = -h(24) -0.015821939 -2-6
h(3) = -h(23) 0 0
h(4) = -h(22) -0.031142897 -2-5-2-12
h(5) = -h(21) 0 0
h(6) = -h(20) -0.056424022 -2-4 + 2-7-2-9
h(7) = -h(19) 0 0
h(8) = -h(18) -0.100431833 -2-3 + 2-5-2-7 + 2-10 + 2-12
h(9) = -h(17) 0 0
h(10) = -h(16) -0.195105144 -2-2 + 2-4-2-7 + 2-12
h(11) = -h(15) 0 0
h(12) = -h(14) -0.630749788 -2-1-2-3-2-7 + 2-9 + 2-12
h(13) 0 0
Figure 1 Frequency response of Hilbert transform FIR filter. Inset showing pass-band ripple.
Duraiswamy et al. EURASIP Journal on Advances in Signal Processing 2011, 2011:32
http://asp.eurasipjournals.com/content/2011/1/32
Page 2 of 5
simple bit shifting of the input signal X(n) to the right
for a specific number of positions to get the various
shifted signals which forms the input to the coefficient
add/sub block. In Figure 2, the bit shifts are denoted by
“ > > “ symbols and the input X(n) is represented in 14
bits. Making use of the symmetric nature of the coeffi-
cients, h(14)-h(26) are realized using adders/subtractors
that make up the coefficient add/sub block and the coef-
ficients h(0)-h(12) are obtained by multiplying by -1.
This reduces the number of multiplications (shifters and
adders/subtractors) to half. There must be at least one
positive digit in the CSD for multiplication implementa-
tion and hence h(14)-h(26) is implemented instead of h
(0)-h(13). The positive coefficients h(14)-h(26) will have
at least one positive digit in the CSD representation. On
the other hand, the negative coefficients may not have
one positive digit in the representation like h(2) and h
(4). Such coefficients require subtraction from zero
which is avoided here. The convectional way of imple-
menting multiplication by -1 is by complementing and
>>2
>>4
>>7
>>12
h(16)
Z-2
0
h(10)
h(12)
Z-2
0
h(14)
Z-2
1
Z-2
1
Coefficient 
Add/Sub
Coefficient
Add/Sub
>>1
>>3
>>7
>>9
>>12
X(n)
To next  
delay
From previous Tap 
adder
a b cin
s
Tap adder
b cina
s
b cina
b cina
s
s
Tap adder
Tap adder
Tap adder
Figure 2 Hardware implementation.
Duraiswamy et al. EURASIP Journal on Advances in Signal Processing 2011, 2011:32
http://asp.eurasipjournals.com/content/2011/1/32
Page 3 of 5
adding one. Here, we use a NOT gate for complement-
ing and the carry of the tap adder is set instead of using
an additional adder for adding one as shown in Figure
2. The setting of the carry in the tap adder eliminates
the need for seven additional adders that are needed to
implement the negative coefficients. One adder is saved
for each negative coefficient implementation and this
reduces the hardware cost compared to the convectional
implementation of the filter with CSD coefficients. A
comparison of the hardware cost for the convectional
CSD and the proposed CSD implementation is shown in
Table 2.
FPGA implementation
The complete filter hardware was described in VHDL
and synthesized using Xilinx ISE 9.2i. The architecture
has a maximum speed of 144 MHz. In order to use it
for digital image rejection of demodulated RF signal, the
proposed architecture is implemented in Virtex-4 FPGA
(XC4VFX20-10FFG672C). For this, a board with the
mentioned FPGA and a USB controller is used. The
input to the FPGA is fed from 14-bit A/D converter
which is clocked at 140 MHz. In order to test the per-
formance of the architecture, it was tested with sinusoi-
dal inputs of three different frequencies. A 7, 13, and 20
MHz sine input was given at the input of the A/D
converter. The phase shifts obtained are 90.7°, 89.98°,
and 89.73°, respectively. The data from FPGA are cap-
tured in the PC and visualized in MATLAB. The phase
shifted output for a 13-MHz sinusoidal input is shown
in Figure 3.
Conclusion
The Hilbert transformer design with CSD coefficients
for determining the impulse response is presented. An
efficient architecture for implementing the filter in
FPGA is presented. By using the symmetric nature of
the filter coefficients, the hardware cost is reduced for
the negative filter coefficient implementation. In the
propose architecture, negative coefficient realization
eliminates the need for additional seven adders com-
pared to the conventional method of CSD FIR filter
implementation.
List of abbreviations
CSD: canonic signed digit; FIR: finite impulse response; IIR: infinite impulse
response.
Competing interests
The authors declare that they have no competing interests.
Received: 7 March 2011 Accepted: 28 July 2011 Published: 28 July 2011
References
1. W Yu, J-m Lai, A fully digital DLLs integrated in FPGAs, in 9th International
Conference on Solid-State and Integrated-Circuit Technology (ICSICT), 3
(2008)
2. A Asoodeh, M Atarodi, A 6-bit active digital phase shifter. IEICE Electron
Express. 8(3), 121–128 (2011). doi:10.1587/elex.8.121
3. D Viveiros Jr, D Consonni, AK Jastrzebski, A tunable all-pass MMIC active
phase shifter. Microwave Theory Tech IEEE Trans. 50(8), 1885–1889 (2002).
doi:10.1109/TMTT.2002.801315
Table 2 Hardware comparison.
Hardware Convectional CSD Proposed CSD
Tap adder 13 13
Delay (Flip-Flop) 26 26
Inverter (NOT gate) 7 7
Adder/subtractor 24 15
0 5 10 15 20 25 30 35 40 45 50
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Samples
A
m
pl
itu
de
Output
Input
Figure 3 Phase shifted output.
Duraiswamy et al. EURASIP Journal on Advances in Signal Processing 2011, 2011:32
http://asp.eurasipjournals.com/content/2011/1/32
Page 4 of 5
4. MS Naghmash, MF Ain, CY Hui, FPGA implementation of software defined
radio model based 16QAM. Eur J Sci Res. 35(2), 301 (2009)
5. H Shekhar, CB Mahto, N Vasudevan, FPGA implementation of tunable FFT
for SDR receiver. IJCSNS Int J Comput Sci Netw Secur. 9(5), 186–190 (2009)
6. C Thomos, G Kalivas, FPGA-based architecture of a DS-UWB Channel
Estimator and RAKE Receiver employing a hybrid selection scheme, in 2010
IEEE 17th International Conference on Telecommunications (ICT), 903–909
(April 2010)
7. RN Gorgui-Naguib, SS Dlay, Hardware implementation of a Hilbert
transformer, in Proceedings of IEEE Mediterranean Electrotechnical Conference
(MELECON’91), 404–407, (May 1991)
8. S He, M Torkelson, FPGA implementation of FIR filters using pipelined bit-
serial canonical signed digit multipliers, in Proceedings of IEEE Custom
Integrated Circuits Conference (CICC’94), 81–84, (May 1994)
9. Y Takahashi, T Kitajima, K Takahashi, Hilbert transformer design using CSD
FIR filter, in Proceedings of 2001 International Technical Conference on
Circuits/Systems Computers and Communications (ITC-CSCC 2001), pp.
921–924, (July 2001)
10. JGRC Gomes, A Petraglia, An analog sampled-data DSB to SSB converter
using recursive Hilbert transformer for accurate I and Q channel matching.
IEEE Trans Circuit Syst II. 49(3), 177–186 (2002). doi:10.1109/
TCSII.2002.1013864
11. H Samueli, An improved search algorithm for the design of multiplier less
FIR filters with powers—of- two coefficients. IEEE Trans Circuits Syst. 36,
1044–1047 (1989). doi:10.1109/31.31347
12. T Cooklev, A Nishihara, Maximally flat Hilbert transformers. Int J Circuit
Theory Appl. 21, 563–570 (1993). doi:10.1002/cta.4490210607
doi:10.1186/1687-6180-2011-32
Cite this article as: Duraiswamy et al.: Efficient implementation of 90°
phase shifter in FPGA. EURASIP Journal on Advances in Signal Processing
2011 2011:32.
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RESEARCH Open AccessEfficient implementation of 90° phase shifterin FPGAPunithavathi Duraiswamy*, Johan Bauwelinck and Jan VandewegeAbstractIn this article, we present an efficient way of implementing 90° phase shifter using Hilbert transformer with canonicsigned digit (CSD) coefficients in FPGA. It is implemented using 27-tap symmetric finite impulse response (FIR)filter. Representing the filter coefficients by CSD eliminates the need for multipliers and the filter is implementedusing shifters and adders/subtractors. The simulated results for the frequency response of the Hilbert transformerwith infinite precision coefficients and CSD coefficients agree with each other. The proposed architecture requiresless hardware as one adder is saved for the realization of every negative coefficient compared to convectional CSDFIR filter implementation. Also, it offers a high accuracy of phase shift.IntroductionPhase shifters have wide spread applications [1-3], inparticular, 90° phase shifters are used in wireless com-munication for single side band generation, IQ modula-tion and image rejection. Digital implementation of 90°phase shifters is in high demand as many of the digitalcommunication systems use FPGAs [4-6]. The FPGAsoffer a wide range of performance for implementingDSP algorithms and hence it is important to efficientlymap the algorithm in order to optimize the area andspeed. Hilbert transformer is the most widely used 90°phase shifter implemented either by a finite impulseresponse (FIR) [7-9] or by an infinite impulse response(IIR) filter [10]. Since the Hilbert transformer is requiredto shift the phase by 90° over a wide range of frequen-cies, FIR filter with linear phase is preferred over IIR fil-ter. The conventional method of implementing the FIRfilter is by adders/subtractors and multipliers. The com-putational time of a multiplier is more than that of anadder/subtractor and also occupies more hardware. Inorder to increase the speed and reduce the hardwarecost, the coefficients of the filter are represented incanonic signed digits (CSD), which is the representationof the coefficients in powers of two. The resulting FIRfilter can be implemented using shifters and adders/sub-tractors without multipliers. The CSD coefficients haveminimum number of non-zero values when comparedto other radix-2 representations which in turn againreduces the number of adders [11]. In this article, anefficient way of implementing the FIR filter with CSDcoefficients is proposed which reduces the number ofadders/subtractors compared to the convectional way ofimplementing the filter with CSD coefficients. In ourapplication, this 90° phase shifter is used for digitalimage rejection of a demodulated RF signal on the recei-ver side of a wireless communication system.CSD representation of filter coefficientsEncoding a binary number such that it contains the few-est number of non-zero bits is called canonic signeddigit (CSD). It maps a number to a ternary system{-1,0,1} versus a binary system {0,1}. The following arethe properties of CSD numbers:No two consecutive bits in a CSD number are non-zero.The CSD representation of a number contains theminimum possible number of non-zero bits, thus thename canonic.The CSD representation of a number is unique.Among the N-bit CSD numbers in the range [-1,1], theaverage number of non-zero bits is N/3 + 1/9 + O(2 -N).Hence, on average, CSD numbers contain about 33%fewer non-zero bits than two’s complement numbers[11]. Now the multipliers in the digital filters are rea-lized using shifters and adders/subtractors. This resultsin the area reduction for digital filters. Here, the* Correspondence: punithavathi@intec.ugent.beGhent University, INTEC/IMEC, Sint-pietersnieuwstraat 41, 9000 Ghent,BelgiumDuraiswamy et al. EURASIP Journal on Advances in Signal Processing 2011, 2011:32http://asp.eurasipjournals.com/content/2011/1/32© 2011 Duraiswamy et al; licensee Springer. This is an Open Access article distributed under the terms of the Creative CommonsAttribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction inany medium, provided the original work is properly cited.complexity of a digital filter is a function of the numberof non-zero digits in the filter coefficient. Encoding thefilter coefficient using the CSD representation reducesthe number of partial products as well as the area andthe power consumption. Hence, it is a useful techniquefor implementing FIR Filters with fixed coefficients.Digital FIR filters can take advantage of this CSDrepresentation.In order to simplify the hardware, the filter is designedwith coefficients represented by powers of two (CSD).The following are the specifications used for the FIR fil-ter design.• Symmetry: Negative• Sampling frequency: 140 MHz• Pass band (normalized): 0.1-0.9• Number of taps: 27• Pass band ripple: 0.1 dB• Stop band attenuation: 50 dB• Coefficients precision: 12 bits• CSD precision: 2The following steps are followed for the design inMATLAB:(1) Determine the filter coefficients using Parks-McClellan FIR filter.(2) Convert the filter coefficients to finite precisioncoefficients.(3) Represent each coefficient in CSD using the algo-rithm in [11].The Parks-McClellan algorithm is optimal in min-maxsense, however, suffers from pass band ripples. Forapplications that require zero ripple in the pass bandand small transition bandwidth, maximally flat FIR fil-ters can be used which have zero ripple in the passband [12]. The coefficient precision can be varied tillthe response is close to the infinite precision frequencyresponse. The number of taps as well as the digits inthe CSD is kept minimum for efficient hardware imple-mentation. The number of taps is varied till the desiredresponse is obtained. The number of filter taps afteroptimization is 27 and the CSD coefficient precision is12 bits. Table 1 gives the CSD coefficients generatedfrom the algorithm in [11] from MATLAB. The fre-quency response of the Hilbert transform with infiniteprecision coefficients and CSD coefficients are shown inFigure 1 and they agree with each other.Hardware architectureThe proposed hardware architecture is shown in Figure2. The architecture consists of two basic blocks: coeffi-cient add/sub and tap adder. The delays are modeled asFlip-Flop.Direct Form II filter architecture is chosen for imple-mentation. Negative powers of two is equivalent to divi-sion by powers of two and can be implemented byTable 1 CSD representation of filter coefficients.Coefficient Value CSD representationh(0) = -h(26) -0.00774850 -2-7 + 2-12h(1) = -h(25) 0 0h(2) = -h(24) -0.015821939 -2-6h(3) = -h(23) 0 0h(4) = -h(22) -0.031142897 -2-5-2-12h(5) = -h(21) 0 0h(6) = -h(20) -0.056424022 -2-4 + 2-7-2-9h(7) = -h(19) 0 0h(8) = -h(18) -0.100431833 -2-3 + 2-5-2-7 + 2-10 + 2-12h(9) = -h(17) 0 0h(10) = -h(16) -0.195105144 -2-2 + 2-4-2-7 + 2-12h(11) = -h(15) 0 0h(12) = -h(14) -0.630749788 -2-1-2-3-2-7 + 2-9 + 2-12h(13) 0 0Figure 1 Frequency response of Hilbert transform FIR filter. Inset showing pass-band ripple.Duraiswamy et al. EURASIP Journal on Advances in Signal Processing 2011, 2011:32http://asp.eurasipjournals.com/content/2011/1/32Page 2 of 5simple bit shifting of the input signal X(n) to the rightfor a specific number of positions to get the variousshifted signals which forms the input to the coefficientadd/sub block. In Figure 2, the bit shifts are denoted by“ > > “ symbols and the input X(n) is represented in 14bits. Making use of the symmetric nature of the coeffi-cients, h(14)-h(26) are realized using adders/subtractorsthat make up the coefficient add/sub block and the coef-ficients h(0)-h(12) are obtained by multiplying by -1.This reduces the number of multiplications (shifters andadders/subtractors) to half. There must be at least onepositive digit in the CSD for multiplication implementa-tion and hence h(14)-h(26) is implemented instead of h(0)-h(13). The positive coefficients h(14)-h(26) will haveat least one positive digit in the CSD representation. Onthe other hand, the negative coefficients may not haveone positive digit in the representation like h(2) and h(4). Such coefficients require subtraction from zerowhich is avoided here. The convectional way of imple-menting multiplication by -1 is by complementing and>>2>>4>>7>>12h(16)Z-20h(10)h(12)Z-20h(14)Z-21Z-21Coefficient Add/SubCoefficientAdd/Sub>>1>>3>>7>>9>>12X(n)To next  delayFrom previous Tap addera b cinsTap adderb cinasb cinab cinassTap adderTap adderTap adderFigure 2 Hardware implementation.Duraiswamy et al. EURASIP Journal on Advances in Signal Processing 2011, 2011:32http://asp.eurasipjournals.com/content/2011/1/32Page 3 of 5adding one. Here, we use a NOT gate for complement-ing and the carry of the tap adder is set instead of usingan additional adder for adding one as shown in Figure2. The setting of the carry in the tap adder eliminatesthe need for seven additional adders that are needed toimplement the negative coefficients. One adder is savedfor each negative coefficient implementation and thisreduces the hardware cost compared to the convectionalimplementation of the filter with CSD coefficients. Acomparison of the hardware cost for the convectionalCSD and the proposed CSD implementation is shown inTable 2.FPGA implementationThe complete filter hardware was described in VHDLand synthesized using Xilinx ISE 9.2i. The architecturehas a maximum speed of 144 MHz. In order to use itfor digital image rejection of demodulated RF signal, theproposed architecture is implemented in Virtex-4 FPGA(XC4VFX20-10FFG672C). For this, a board with thementioned FPGA and a USB controller is used. Theinput to the FPGA is fed from 14-bit A/D converterwhich is clocked at 140 MHz. In order to test the per-formance of the architecture, it was tested with sinusoi-dal inputs of three different frequencies. A 7, 13, and 20MHz sine input was given at the input of the A/Dconverter. The phase shifts obtained are 90.7°, 89.98°,and 89.73°, respectively. The data from FPGA are cap-tured in the PC and visualized in MATLAB. The phaseshifted output for a 13-MHz sinusoidal input is shownin Figure 3.ConclusionThe Hilbert transformer design with CSD coefficientsfor determining the impulse response is presented. Anefficient architecture for implementing the filter inFPGA is presented. By using the symmetric nature ofthe filter coefficients, the hardware cost is reduced forthe negative filter coefficient implementation. In thepropose architecture, negative coefficient realizationeliminates the need for additional seven adders com-pared to the conventional method of CSD FIR filterimplementation.List of abbreviationsCSD: canonic signed digit; FIR: finite impulse response; IIR: infinite impulseresponse.Competing interestsThe authors declare that they have no competing interests.Received: 7 March 2011 Accepted: 28 July 2011 Published: 28 July 2011References1. W Yu, J-m Lai, A fully digital DLLs integrated in FPGAs, in 9th InternationalConference on Solid-State and Integrated-Circuit Technology (ICSICT), 3(2008)2. A Asoodeh, M Atarodi, A 6-bit active digital phase shifter. IEICE ElectronExpress. 8(3), 121–128 (2011). doi:10.1587/elex.8.1213. D Viveiros Jr, D Consonni, AK Jastrzebski, A tunable all-pass MMIC activephase shifter. Microwave Theory Tech IEEE Trans. 50(8), 1885–1889 (2002).doi:10.1109/TMTT.2002.801315Table 2 Hardware comparison.Hardware Convectional CSD Proposed CSDTap adder 13 13Delay (Flip-Flop) 26 26Inverter (NOT gate) 7 7Adder/subtractor 24 150 5 10 15 20 25 30 35 40 45 50−1−0.8−0.6−0.4−0.200.20.40.60.81SamplesAmplitudeOutputInputFigure 3 Phase shifted output.Duraiswamy et al. EURASIP Journal on Advances in Signal Processing 2011, 2011:32http://asp.eurasipjournals.com/content/2011/1/32Page 4 of 54. MS Naghmash, MF Ain, CY Hui, FPGA implementation of software definedradio model based 16QAM. Eur J Sci Res. 35(2), 301 (2009)5. H Shekhar, CB Mahto, N Vasudevan, FPGA implementation of tunable FFTfor SDR receiver. IJCSNS Int J Comput Sci Netw Secur. 9(5), 186–190 (2009)6. C Thomos, G Kalivas, FPGA-based architecture of a DS-UWB ChannelEstimator and RAKE Receiver employing a hybrid selection scheme, in 2010IEEE 17th International Conference on Telecommunications (ICT), 903–909(April 2010)7. RN Gorgui-Naguib, SS Dlay, Hardware implementation of a Hilberttransformer, in Proceedings of IEEE Mediterranean Electrotechnical Conference(MELECON’91), 404–407, (May 1991)8. S He, M Torkelson, FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers, in Proceedings of IEEE CustomIntegrated Circuits Conference (CICC’94), 81–84, (May 1994)9. Y Takahashi, T Kitajima, K Takahashi, Hilbert transformer design using CSDFIR filter, in Proceedings of 2001 International Technical Conference onCircuits/Systems Computers and Communications (ITC-CSCC 2001), pp.921–924, (July 2001)10. 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EURASIP Journal on Advances in Signal Processing2011 2011:32.Submit your manuscript to a journal and benefi t from:7 Convenient online submission7 Rigorous peer review7 Immediate publication on acceptance7 Open access: articles freely available online7 High visibility within the fi eld7 Retaining the copyright to your article    Submit your next manuscript at 7 springeropen.comDuraiswamy et al. EURASIP Journal on Advances in Signal Processing 2011, 2011:32http://asp.eurasipjournals.com/content/2011/1/32Page 5 of 5