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EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures
Authors
M Al Kadi
T Becker
+17 more
A Brokalakis
G Charitopoulos
CB Ciobanu
G Gaydadjiev
M Huebner
A Kulkarni
W Luk
A Nikitakis
X Niu
D Pnevmatikatos
MD Santambrogio
D Sciuto
D Stroobandt
AJW Thom
T Todman
E Vansteenkiste
AL Varbanescu
Publication date
1 January 2016
Publisher
2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2016
Doi
Cite
Abstract
© 2016 IEEE. To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on. EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field
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