Heterogeneous multi-core processors have become the mainstream solution for current computer platforms owing to their high performance, low power consumption, and wide range of application scenarios. In addition, the large-capacity Static Non-Uniform Cache Architecture(S-NUCA) has a low average access time. However, the rising transistor size results in challenges to the resource scheduling and power control of heterogeneous multi-core processors. Traditional scheduling algorithms ignore the cache access latency between cores despite S-NUCA-based multi-core processors, and traditional thermal management schemes only provide chip-level power constraints, which easily degrade the system performance owing to low core utilization. In this study, we propose Thermal Security Constrained Dynamic Mapping(TSCDM), a dynamic thread scheduling mechanism for S-NUCA heterogeneous multi-core systems that satisfies thermal security constraints. TSCDM utilizes a phase detection technique based on dynamic Instructions Per Clock(IPC) values. It predicts the IPC values of threads based on Artificial Neural Network(ANN) to obtain the optimal binding relationship between threads and core types and obtain optimal mapping and task migration policies based on task classification according to S-NUCA cache characteristics. Finally, TSCDM allocates power budgets for each core in real time based on the on-chip thermal model. The results of running the SPLASH-2 performance test suite on HotSniper demonstrate that TSCDM achieves advantages in both speedup ratio and resource utilization compared to traditional scheduling schemes and other machine learning-based scheduling schemes. Moreover, the employed Transient-Temperature Based Safe Power(T-TSP)algorithm further reduces the core thermal headroom than the traditional Thermal Safe Power(TSP) algorithm, while the processor has a higher energy efficiency ratio across the full frequency band
