Network-on-Chip (NoC) has been shown to be the most

viable alternative to an interconnect bus for the scalability

of the system [1]. On-chip antennas, implementing wireless

interconnects, are introduced for improved scalability of

NoCs in [2]. On-chip wireless links offer improved network

performance due to long distance communication, additional

bandwidth, and broadcasting capabilities of antennas. The

most prominent on-chip antenna designs are the planar logperiodic

and meander which have a surface-propagation of

the EM waves of the antenna. The main detriment of these

antennas, and surface-propagation in general, is the poor

signal attenuation (i.e. path loss) even at small distances

of 5mm. This work challenges the on-chip antenna design

conventions, and pushes toward a Through-Silicon Via (TSV)-

based antenna design called TSV_A that establishes wireless

communication through the silicon substrate medium with

only a 3 dB loss over a 30mm on-chip distance

Dandekar, Kapil R.

Liu, Yuqiao

Pano, Vasil

Taşkın, Barış

Tekin, İbrahim

English

Sabanci University Research Database

In-Package Wireless Communication withTSV-based AntennaVasil Pano*, Ibrahim Tekin†, Yuqiao Liu*, Kapil R. Dandekar*, and Baris Taskin**Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104, USA†Electronics Engineering, Sabanci University, 34956 Orhanli, Istanbul, TurkeyI. INTRODUCTIONNetwork-on-Chip (NoC) has been shown to be the mostviable alternative to an interconnect bus for the scalabilityof the system [1]. On-chip antennas, implementing wire-less interconnects, are introduced for improved scalability ofNoCs in [2]. On-chip wireless links offer improved networkperformance due to long distance communication, additionalbandwidth, and broadcasting capabilities of antennas. Themost prominent on-chip antenna designs are the planar log-periodic and meander which have a surface-propagation ofthe EM waves of the antenna. The main detriment of theseantennas, and surface-propagation in general, is the poorsignal attenuation (i.e. path loss) even at small distancesof 5mm. This work challenges the on-chip antenna designconventions, and pushes toward a Through-Silicon Via (TSV)-based antenna design called TSV_A that establishes wirelesscommunication through the silicon substrate medium withonly a 3 dB loss over a 30mm on-chip distance.II. DESIGN OF TSV ANTENNAThe design of the proposed antenna is based on a typicaldisc-loaded monopole antenna. A TSV acts as the main radi-ating part of the monopole antenna: A novel on-chip antennadesign labeled TSV_A, shown in Figure 1. A small optionalcylindrical disc of copper at the bottom of the TSV_A canbe used for impedance matching to improve the overall signalstrength.CPWCuCuFig. 1. The structure of the TSV_A in HFSS.The TSV_A is placed inside the layer of silicon (Si) sub-strate. In HFSS simulations, the TSV material and cylindricaldisc is selected to be copper (Cu), however any conductivematerial in varying TSV implementations could theoretically60 61 62 63 64 65 66 67 68 69 70Frequency (GHz)-35-30-25-20-15-10-50S Parameters (dB)TSV_A - S(1,1)TSV_A - S(2,1)Lower Bound: 63.5 GHzUpper Bound: 68.5 GHzInsertion Loss: -1.4 dBFig. 2. S-parameters of TSV_A pair.be used as the main radiating part of the monopole antenna.In simulations, the relative dielectric constant (ε r) used forthe Si substrate is 11.7.III. EVALUATION OF TSV_AS-parameters describe the input-output relationship betweenantennas, characterizing the channel to identify the frequencyand bandwidth of transmission. Return loss (S11) representshow much power is reflected from the TSV_A (lower isbetter). Insertion loss (S21) represents the power receivedat the second TSV_A (higher is better). S-parameters for apair of TSV_A communicating at 5mm distance are shown inFigure 2. The TSV_A pair are communicating at a distanceof 5mm and a bandwidth of 5 GHz can be achieved in the63.5 to 68.5 GHz frequency range. The insertion loss (S21)in that range peaks at 1.5 dB and on average it is 2.3 dB.The insertion loss of TSV_A at greater distances (up to 30mmtested) remains ≈3 dB.IV. CONCLUSIONSThis work proposes a novel communication infrastructure,utilizing TSVs for on-chip wireless communication. FEMsimulations are performed to validate the operation of the TSVantenna (TSV_A). Simulation results indicate that the TSV_Ais capable of transmission up to 30mm distance at a minimalinsertion loss of ≈3 dB, which is a substantial improvementover current on-chip wireless antennas.V. RELATED WORKSThe feasibility of on-chip wireless antennas is studied by K.Kim [3, 4]. Lin et al. [5] demonstrate fabricated (90nm–130nmtechnology) antennas to be fully operational. Yu et al. [6]propose (and fabricated in 65nm bulk CMOS process) an on-off keying (OOK) transceiver which consume only 1.2 pJ/bitat a data rate of 16 Gb/s operating at 60 GHz. Substratepropagation dipole antennas are achieved by placing verticalundoped silicon layers connected to the substrate underneath,in [7]. These vertical layers adversely affects the floorplan ofactive devices on chip (limiting utilization and prohibiting theuse of sides).VI. SUPPLEMENTAL MATERIALAn illustrative (not to scale) representation of two TSV_Acommunicating is shown in Figure 3. The FEOL and BEOLlayers are compliant with common manufacturing processesas well as modern ASIC flow, with no influence on thoseprocesses, other than the TSVs reserved for wireless com-munication. The silicon substrate layer under the active layeracts as a waveguide for the signal. Fabrication of the TSV_Afollows the standard 3D-IC procedures for typical TSVs.Path loss analysis of the TSV_A is performed in Sec-tion VI-A. Analyses of the interference between TSV_As,including those with TSVs, are presented in Section VI-B.Feasibility study of TSV_A is detailed in Section VI-C.FEOL; active layern+n+Sin+n+BEOL; metal layersTSV_A Wireless WaveguideTx RxFig. 3. Illustration of die cross-section with 2 TSV As.A. Path Loss AnalysisPath loss is a major component in the characterization oftransmission distance and power consumption, and representsthe reduction of the input power as the EM field propagatesthrough the substrate. Path loss analysis is performed for theTSV_A and compared against the planar log-periodic [8] andmeander [9] antenna. The results of the evaluation are shownin Figure 4. The two TSV_As (Tx and Rx) are placed atincreasing distances (1.25mm–30mm) from each other and thetransmission coefficient (S21) is recorded from the HFSS FEMsimulations. The TSV_A has an almost constant and very low3 dB path loss due to the undoped silicon substrate layer actingas a wireless waveguide for the signal. The planar log-periodicand meander antennas suffer from exponential increase in pathloss (up to 40 dB for the meander and up to 35 dB forthe log-periodic antennas) due to the surface-propagation ofthe EM field. Improved path loss leads to several benefits,including: 1) The removal of low-noise amplifiers (LNAs),2) low and constant power consumption, and, 3) increasedTSV_A position flexibility during design-time.1.25 2.5 5 10 15 20 25 30Tx-Rx Distance (mm)-50-45-40-35-30-25-20-15-10-5-30Insertion Coefficient (S21) dBTSV_ALog-periodic antennaMeander antennaFig. 4. Transmission coefficient (S21) versus distance.B. TSV_A Interference from TSVIn Figure 5, two TSV_As are placed on the same board ata distance of 6mm. Multiple randomly placed TSVs are addedbetween the TSV_As to quantify the interference caused fromother TSVs in the system. Multiple structures are evaluatedincluding a sweep of 1 to 4 TSV rows for 3-D memory ap-plications, and additionally one hundred other structures withrandomly placed TSVs on the board, as shown in Figure 5.Return loss (S11) and insertion loss (21) for all obstructionsare shown in Table I. All TSVs have a radius of 20µm andare equally spaced at 225µm in the row structure case. Thereturn and insertion loss of the 100 randomized placements areaveraged together. Without any obstruction, the TSV_As hasa return loss of 16 dB and insertion loss of 2.2 dB. With 3 or4 TSV rows of obstruction, the minimum return and insertionloss are 8.5 dB and 17 dB, respectively.TSV_A 1TSV_A 2TSVsFig. 5. TSV_A pair obstructed by randomly placed TSVs.The average return and insertion loss of the TSV_As withthe randomized TSV obstructions are 15.5 dB and 6.6 dB,respectively. TSV_A is shown to operate with additional TSVsin the silicon substrate layer, and even in the worst-casescenario it performs better than the planar log-periodic [8] andmeander [9] antennas, at ≈20 dB to ≈30 dB at 6mm distance,TABLE I. TSV impact on TSV_A performance.Obstruction Return Loss (S11) Insertion Loss (S21)None 16 dB 2.2 dB1 Row TSV 12 dB 7 dB2 Row TSV 12 dB 12 dB3 Row TSV 8.5 dB 16 dB4 Row TSV 8.5 dB 17 dBRandom 15.5 dB 6.6 dBwithout any interference. For optimal signal performance, thesubstrate layer can be dedicated only to the TSV_As forRF communication. If the silicon substrate layer cannot bededicated to the TSV_As, guidelines can be developed forfloorplanning to minimize interference between TSV_As andtypical TSVs.C. Feasibility Study of TSV_AThe feasibility of the aspect ratio of 5:1 selected in this workfor the TSV_A size is demonstrated in [10, 11]. For example,DRIE [11] is capable of forming a wide range of via holes upto an aspect ratio of 100:5. In addition, the research communityhas investigated the process robustness in-depth, sweeping thevia dimensions from 3-80 µm wide and 45-160 µm deep inin 150mm and 200mm wafers [10]. There is active researchin the manufacturing of TSVs for 3D ICs and interposers.The TSV_As benefit from these packaging and manufacturinginnovations.REFERENCES[1] R. Das, S. Eachempati, A. K. Mishra, V. Narayanan, and C. R. Das,“Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs,” in Proceedings of the IEEE International Symposiumon High Performance Computer Architecture (HPCA), February 2009,pp. 175–186.[2] K. K. O, K. Kim, and B. A. Floyd, “On-chip antennas in silicon ICsand their application,” IEEE Transactions on Electron Devices, vol. 52,no. 7, pp. 1312–1323, July 2005.[3] K. Kim and K. K. O, “Integrated dipole antennas on silicon substrates forintra-chip communication,” in IEEE Antennas and Propagation SocietyInternational Symposium, vol. 3, July 1999, pp. 1582–1585.[4] K. K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C. Hung, D. Bravo,T. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch,D. Yang, J. Bohorquez, J. Chen, E. Seok, L. Gao, A. Sugavanam, J. Lin,S. Yu, C. Cao, M. Hwang, Y. Ding, S.-H. Hwang, H. Wu, N. Zhang,and J. E. Brewer, “The feasibility of on-chip interconnection usingantennas,” in Proceedings of the IEEE/ACM International Conferenceon Computer-Aided Design (ICCAD), November 2005, pp. 979–984.[5] J. J. Lin, H. T. Wu, Y. Su, L. Gao, A. Sugavanam, J. E. Brewer, andK. K. O, “Communication using antennas fabricated in silicon integratedcircuits,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1678–1687, August 2007.[6] X. Yu, J. Baylon, P. Wettin, D. Heo, P. P. Pande, and S. Mirabbasi, “Ar-chitecture and design of multichannel millimeter-wave wireless NoC,”IEEE Design Test, vol. 31, no. 6, pp. 19–28, December 2014.[7] Y. Liu, V. Pano, D. Patron, K. Dandekar, and B. Taskin, “Innovativepropagation mechanism for inter-chip and intra-chip communication,” inProceedings of the IEEE Annual Wireless and Microwave TechnologyConference (WAMICON), April 2015, pp. 1–6.[8] A. Samaiyar, S. S. Ram, and S. Deb, “Millimeter-wave planar logperiodic antenna for on-chip wireless interconnects,” in Proceedings ofthe European Conference on Antennas and Propagation (EuCAP), April2014, pp. 1007–1009.[9] H. Nakano, H. Tagami, A. Yoshizawa, and J. Yamauchi, “Shorteningratios of modified dipole antennas,” IEEE Transactions on Antennasand Propagation, vol. 32, no. 4, pp. 385–386, April 1984.[10] B. Kim, C. Sharbono, T. Ritzdorf, and D. Schmauch, “Factors affectingcopper filling process within high aspect ratio deep vias for 3D chipstacking,” in Proceedings of the Electronic Components and TechnologyConference (ECTC), June 2006, pp. 838–843.[11] M. Puech, J. M. Thevenoud, J. M. Gruffat, N. Launay, N. Arnal,and P. Godinat, “Fabrication of 3D packaging TSV using DRIE,”in Proceedings of the Symposium on Design, Test, Integration andPackaging of MEMS/MOEMS (DTIP), April 2008, pp. 109–114.

In-package wireless communication with TSV-based antenna

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In-package wireless communication with TSV-based antenna

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