International Journal of Electrical and Computer Engineering Research
Abstract
This graduate project is an implementation of an encoder based upon the REED-SOLOMON code, using Very Large Scale Integration or VLSI. The project includes the discussion and use of a parallel pipelined technique, along with the cell block and system architectures. A proof of design and layout on CMOS configurable gate arrays is conducted by computer simulation. And finally, a summary describing the overall results of the implementation including possible improvements is described.Includes bibliographical references (pages 52-54)California State University, Northridge. Department of Engineering.Includes digitized image(s) in TIFF format
