'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Abstract
In this work, a complementary InAs/Al0.05Ga0.95Sb
tunnel field-effect-transistor (TFET) virtual technology platform
is benchmarked against the projection to the CMOS FinFET
10-nm node, by means of device and basic circuit simulations.
The comparison is performed in the ultralow voltage regime
(below 500 mV), where the proposed III\u2013V TFETs feature
ON-current levels comparable to scaled FinFETs, for the same
low-operating-power OFF-current. Due to the asymmetrical
n- and p-type I\u2013Vs, trends of noise margins and performances
are investigated for different Wp/Wn ratios. Implications of the
device threshold voltage variability, which turned out to be
dramatic for steep slope TFETs, are also addressed