Fast Fourier Transformation (FFT) and it's inverse (IFFT) are used in Orthogonal Frequency Division Multiplexing (OFDM) systems for data (de)modulation. The transformations are the kernel tasks in an OFDM implementation, and are the most processing-intensive ones. Recent trends in the electronic consumer market require OFDM implementations to be flexible, making a trade-off between area, energy-efficiency, flexibility and timing a necessity. This has spurred the development of Application-Specific Instruction-Set Processors (ASIPs) for FFT processing. Parallelization is an architectural parameter that significantly influence design goals. This paper presents an analysis of the efficiency of parallelization techniques for an FFT-ASIP. It is shown that existing techniques are inefficient for high throughput applications such as Ultra Wideband (UWB), because of memory bottlenecks. Therefore, an interleaved execution technique which exploits temporal parallelism is proposed. With this technique, it is possible to meet the throughput requirement of UWB (409.6 Msamples/s) with only 4 non-trivial butterfly units for an ASIP that runs at 400MHz. © 2006 IEEE

Arikan, E.

Ascheid G.

Atak O.

Atalar, A.

Ishebabi H.

Meyr H.

Bilkent University Institutional Repository

See	discussions,	stats,	and	author	profiles	for	this	publication	at:	https://www.researchgate.net/publication/224648294An	efficient	parallelization	technique	for	highthroughput	FFT-ASIPsConference	Paper	·	June	2006DOI:	10.1109/ISCAS.2006.1693920	·	Source:	IEEE	XploreCITATIONS5READS626	authors,	including:Harold	IshebabiUniversität	Potsdam18	PUBLICATIONS			140	CITATIONS			SEE	PROFILEOguzhan	AtakASELSAN	Inc.4	PUBLICATIONS			33	CITATIONS			SEE	PROFILEA.	AtalarBilkent	University175	PUBLICATIONS			4,140	CITATIONS			SEE	PROFILEAll	content	following	this	page	was	uploaded	by	A.	Atalar	on	04	October	2017.The	user	has	requested	enhancement	of	the	downloaded	file.An Efficient Parallelization Technique for HighThroughput FFT-ASIPsH. Ishebabi, G. Ascheid, H. MeyrInstitute for Integrated Signal Processing SystemsRWTH Aachen University, Aachen, Germanyishebabi@iss.rwth-aachen.deO. Atak, A. Atalar, E. ArikanDepartment of Electrical and Electronic EngineeringBilkent University, Ankara, Turkeyatak@ee.bilkent.edu.trAbstract— Fast Fourier Transformation (FFT) and it’s inverse(IFFT) are used in Orthogonal Frequency Division Multiplexing(OFDM) systems for data (de)modulation. The transformationsare the kernel tasks in an OFDM implementation, and are themost processing-intensive ones. Recent trends in the electronicconsumer market require OFDM implementations to be flexible,making a trade-off between area, energy-efficiency, flexibilityand timing a necessity. This has spurred the development ofApplication-Specific Instruction-Set Processors (ASIPs) for FFTprocessing. Parallelization is an architectural parameter thatsignificantly influence design goals. This paper presents ananalysis of the efficiency of parallelization techniques for an FFT-ASIP. It is shown that existing techniques are inefficient for highthroughput applications such as Ultra Wideband (UWB), becauseof memory bottlenecks. Therefore, an interleaved executiontechnique which exploits temporal parallelism is proposed. Withthis technique, it is possible to meet the throughput requirementof UWB (409.6 Msamples/s) with only 4 non-trivial butterfly unitsfor an ASIP that runs at 400MHz.I. INTRODUCTIONOrthogonal Frequency Division Multiplexing (OFDM) isa multi-carrier modulation technique that has been adoptedin various wireless communication standards such as Wire-less Local Area Networks (WLAN), Digital Video Broad-casting (DVB) and OFDM-based Ultra Wideband (UWB).The (de)modulation process uses Fast Fourier Transformation(FFT) and it’s inverse (IFFT). These transformations are themost computationally intensive tasks in an OFDM system [1].Flexibility is a key requirement in wireless systems beyond3G (B3G) [2], where modems can be reprogrammed orreconfigured to support different radio standards and operatingmodes. Consequently, Application Specific Instruction SetProcessors (ASIPs) and Digital Signal Processor (DSPs) withspecial support for FFT processing have been developed tomeet both flexibility and processing time constraints [3], [4].In ASIPs, parallelization can be used to meet timing re-quirements (throughput). However, the type and degree ofparallelization influence the efficiency of the implementation;both with respect to energy dissipation and area utilization.Therefore, we analyzed the efficiency of parallelization tech-niques under high throughput requirements, when appliedto FFT-ASIPs. Area and energy consumption were taken asa measure of efficiency. The intention was to single out aparallelization technique with an outstanding efficiency forexploitation in FFT-ASIPs.There is a substantial amount of publications on FFT par-allelization, however, the focus has been on general purpose,parallel and distributed computing domains. The recent emer-gence of methodology and tools for architecture explorationand automatic implementation such as LISA-based tools [5]enables this kind of analysis to be conducted for FFT-ASIPsas well.The analysis reveals that existing parallelization techniquesat the instruction and data level cannot efficiently meet high-throughput requirements such as 409.6 Msamples/s for UWB.This is caused by memory bottlenecks. Therefore, we proposethe use of an interleaved execution technique which is capableof hiding some of the stage execution cycles by exploitingtemporal parallelism. In this analysis, UWB was selected todemonstrate that it is feasible to implement instruction-setprocessors which can efficiently support, among other things,the computation of high-rate FFTs.The rest of the paper is organized as follows: the imple-mented FFT algorithm and the FFT-ASIP architecture foranalysis are presented in section II. The analysis for instructionand data level parallelization techniques are presented insections III, followed by the proposed interleaved techniquein sections IV and V. Concluding remarks are provided insection VI.II. THE FFT ALGORITHM AND THE FFT-ASIPThe Cooley-Tukey (CT) [6] algorithm has been widelyadopted for FFT computation because of it’s regularity. Acached FFT (CFFT) algorithm which enables the exploita-tion of data locality for energy-efficient implementations wasproposed in [7]. Figure 1 shows a comparison of energyconsumption of two ASIPs for the two FFT algorithms. TheASIPs are described in detail in [8] and [9] respectively.Because of higher energy-efficiency, the CFFT-ASIP wasselected for analysis. This ASIP is similar to the CT-ASIP:it has the same pipeline length, the same data-path width,the same memory configuration, and a butterfly instruction.This instruction calculates the addresses of the coefficients anddata samples, fetches the operands, and computes the completebutterfly with a latency of 6 clock cycles. The maximum clockfrequency of the ASIP is 250MHz. In the ASIP, a 32x32register file is used as a cache. Both ASIPs were designed and 0.1 1 10 200  400  600  800  1000E/uJNEnergy Consumption for FFT Computation on Dedicated ASIPsCooley-TukeyCached FFTE/uJFig. 1. Energy dissipation of CT and CFFT ASIPsimplemented by using the same design flow and technology[8], [9].In the cached algorithm, the FFT computation is dividedinto Epochs (E), Groups (G) and Passes (P) [7]. The followingpseudo-code shows how the algorithm is implemented.FOR e = 0 to E-1FOR g = 0 to G-1Load_Cache(e,g);FOR p = 0 to P-1FOR b = 0 to NumBFLY-1Butterfly(e,g,p,b);ENDENDDump_Cache(e,g);ENDENDIn this analysis, a modified version of the algorithm with abetter cache utilization is used [9]. A better cache utilizationis achieved through an uneven distribution of passes betweenthe epochs. Figure 2 shows the flow graph for N=64 (cachesize=16).III. ANALYSIS OF EXISTING PARALLELIZATIONTECHNIQUESOn the architectural level, existing techniques can begrouped into Instruction, Data and Thread-Level Paralleliza-tion (ILP,DLP and TLP). Basically, the latter technique is use-ful for time-multiplexing the processor usage. Consequently,TLP cannot be used to increase the throughput of FFTcomputation on a dedicated ASIP.Besides pipelining, ILP can be categorized according toinstruction issue size: single and multiple issue. The lattercan be further categorized into explicit (e.g. complex or fusedinstructions), static (e.g. VLIW) and dynamic issue (e.g. superscalar). However, since power consumption is a limiting factor,particularly for battery-powered modems, a dynamic issuingscheme is not considered.Generally, longer pipelines increase the throughput of a pro-cessor. However, the analysis of power/performance metricsFig. 2. Data flow graph of the CFFT algorithm for N=64with pipeline length shows that as the power consumptionbecomes more important in the metric, shorter pipelines tendto yield optimum results [10]. Since in this case powerconsumption is a concern, short pipelines are preferred. Nev-ertheless, by using more complex instructions (higher explicit-ness), a high throughput can be obtained with short pipelines.For a radix-2 FFT implementation, a butterfly instruction asdescribed in section II offers the highest degree of explicitparallelization. However, this is not sufficient for meeting thethroughput requirement as shown below.In the CFFT-ASIP, the 4ns long critical path goes throughthe butterfly unit. The unit is distributed over three pipelinestages. By adding two additional stages, the critical path can beshortened to 2.5ns. In figure 3, the throughput of the ASIP isdepicted for several FFT lengths. Clearly, the timing constraintfor UWB cannot be met, even when a non-favorable 1ns clockis assumed to be possible.For the last ILP alternative, the architecture was extendedby three slots, so that four butterflies could be computed inparallel. Because of data dependencies between the passes [9],only a speed-up factor of 1.73 was achieved for N=128, whichwas far less than the required 11.41. This speed-up factorcannot be achieved by increasing the number of slots furtherdue to a limited memory bandwidth, even with a 400MHzclock, since only 312.5ns/2.5ns=125 cycles are available forFFT processing (312.5ns is the OFDM symbol length inUWB). This is because cache loading and dumping alonealready consume 256 cycles. The reason for this is the orderof computation.The FFT computation proceeds as shown in figure 4. Inthis case, there are 2 epochs, 4 groups and 7 passes. Thegroups are computed consecutively (0-3). In each group, thepasses are computed in the order 0-4 for epoch 0, and 5-6 for epoch 1. Epoch 0 is computed first. Cache loadingis done in passes 0 and 5, and the dumping in passes 4 0.1 1 10 100 0  100  200  300  400  500  600  700  800  900  1000  1100micro secNFFT Computation Time for the CFFT-ASIPUWBWLANDABWiMAX4ns Clock Period2.5ns Clock Period (projected)micro secmicro secFig. 3. FFT computation time for CFFT-ASIPand 6. Cache dumping is done concurrently with Non-TrivialButterfly (NBF) computation. In epoch 0, cache loading is alsoconcurrently done, however, the butterflies are trivial since inall cases the coefficient is 1+0i, where i =√−1. In epoch 1,the cache is separately loaded. Since a dual port data memorywas used, 256 cycles were needed loading and dumping.The memory bandwidth can be increased by partitioning thememory with a similar scheme as in [11]. If, for instance, 32data samples (cache size) can be accessed concurrently, thenat least448 butterfly cycles − 64 trivial butterfly cycles125 cycles − 56 control cycles − 8 load/dump cycles = 7NBF units would be required to achieve the throughput at400MHz, with a correspondingly very high area and energyconsumption. This is the minimum number of NBF units. Amixed-radix approach such as [12] would lead to a low areacost because of higher-radix. However, a similar approach isnot applicable in this case for flexibility reasons.For DLP, the analysis and the results are similar to thepreceding ones. The difference is that in DLP techniques suchas vector instructions, only one instruction would be decoded,rather than 7 as in the above 7-slot VLIW.A careful analysis of computation order reveals that it ispossible to interleave the execution, so that the throughputis achieved with only 4 NBF units, and with no memorypartitioning. This technique is described in the followingsection.IV. INTERLEAVED EXECUTIONThe idea behind interleaved execution is to hide some of theexecution cycles through instruction scheduling. This means,as opposed to ILP techniques, temporal parallelism betweenthe passes is exploited, rather than spatial parallelism in thegroups. In subsequent discussion, a latency of 3 cycles for theactual execution of a butterfly is assumed.With the preceding ILP technique in section III, the order ofcomputation (figure 4) is G0 : P0−P4, G1 : P0−P4, · · · , G3 :P0 − P4, G0 : P5 − P6, · · · , G3 : P5 − P6 [7], [9]. TableI shows the cache addressing for N=128 [7], [9]. The starFig. 4. CFFT computation order for N=128TABLE ICACHE ADDRESSING FOR N=128Epoch Pass Cache Address0 0 B3 B2 B1 B0 *1 B3 B2 B1 * B02 B3 B2 * B1 B03 B3 * B2 B1 B04 * B3 B2 B1 B01 3 B3 * B2 B1 B04 * B3 B2 B1 B0in the table has the values 0 and 1 for the two data of thebutterfly respectively. The pass number determines the positionof the star. With this table, and with the pipeline model, itfollows that the first 2 operands for computation of G0 : P1are available 3 cycles after G0 : P0 has started. The next 2 after4 cycles, etc. Similarly, for G0 : P2, the operands are available6, 7, 8, · · · cycles after G0 : P1 has started, etc. Therefore, theexecution can be interleaved as shown in figure 5. The nextgroup (G1 : P0) cannot start until the first 2 cache elementshas been dumped in G0 : P4. However, because of a latencyof 3 cycles, the next loading can start 2 cycles prior to thedumping as shown in the figure. In this way, epoch 0 can beprocessed in 105 cycles. Similarly, epoch 1 can be finishedin 48 cycles, making a total of 153 cycles for N=128, so thatthe cycle constraint from section II is violated by 153-125=28cycles. This is largely attributed to 13 cycles between eachcache loading between the groups (greyed area in figure 5). Ifthese 13 cycles are removed, then the total number of cyclescan be reduced by 13x3=39.Since in each cycle Bload loads 2 cache registers, addi-tional 26 cache registers are required. This would only addapproximately 30KGates to the CFFT-ASIP, which has, inthe current version, 430KGates (of which 63% are occupiedby memories). To simplify cache addressing in presence ofadditional buffering registers, a modulo addressing scheme canbe used.The execution of control and initialization instructions canalso be interleaved, so that the associated cycles are completelyhidden. This technique requires a different instructions execu-tion sequencing. A corresponding execution model is proposedin the following section.Fig. 5. Interleaving schemeV. EXECUTION MODELIn mainstream processor architectures, each execution isimmediately preceded by instruction fetching and decoding inabsence of hazards. Therefore, with such an execution model,it is not possible to interleave instructions without having tounroll all iterations. A data-triggered execution model cansolve this problem. A Transport Triggered Architecture (TTA)which is data-triggered is proposed in [13]. However, TTAtargets at reducing bypass complexity, rather than exploitingtemporal parallelism.Therefore, the following execution model is proposed: Afterfetching and decoding, an execution unit is conditionallyscheduled for execution. The condition is specified by theprogrammer. If scheduled for execution, the correspondingoperation remains pending until another condition is fulfilled.The latter is internally generated in the processor by otherinstructions, similarly to flags setting. Such a condition couldfor instance be the availability of operands (data-triggering).The pending operation does not block the further sequencingof instructions, rather, it enters a pending slot, while theprocessor continues to fetch and decode other instructions. Theexecution condition is polled in each cycle until it becomestrue. Thereafter, the operation is executed concurrently toany other activated operation. After execution, the conditionis automatically toggled back to false, and the operation isemptied from the pending slot.In this execution model, Zero Overhead Loops (ZOLs)are non-blocking, i.e. when the initialization of a ZOL isencountered, the ZOL is started, and the following instructionis fetched. If the following instruction has to wait, then thesequencing of instruction has to be explicitly suspended, untila required condition is fulfilled.VI. SUMMARY AND CONCLUSIONIn this paper, it has been shown that existing parallelizationtechniques cannot be efficiently utilized in FFT-ASIPs forhigh throughput applications such as UWB. An interleavedexecution technique which can meet the throughput require-ment is therefore proposed, together with the correspondingexecution model. With this technique, only 4 NBF unitsare required. Currently, we are extending the CFFT-ASIP tosupport interleaved execution. Based on the results of the 4-slotVLIW extension, the area is expected to increase by 28% to550.4KGates (7% due to additional cache registers, 21% dueto additional NBF units). UWB was selected to demonstratethat it is feasible to implement instruction-set processors whichcan efficiently support, among other things, the computationof high-rate FFTs.ACKNOWLEDGEMENTSThis work has been partially funded by the EuropeanCommission through the Network of Excellence in WirelessCOMmunications (Newcom).REFERENCES[1] L. Hanzo, M. Mnster, B. Choi, and T. Keller, OFDM and MC-CDMAfor broadband multi-user communications, WLANs and broadcasting.Chichester, UK: Wiley, 2003.[2] J. Mitola, Software radio architecture : object-oriented approaches towireless systems engineering. New York: Wiley, 2000.[3] K. Heo, S. Cho, J. Lee, and M. Sunwoo, “Application-specific dsparchitecture for fast fourier transform,” in IEEE International Conferenceon Application-Specific Systems, Architectures, and Processors, June2003, pp. 369– 377.[4] CARMEL DSP Core Data Sheet, Infineon Technologies Inc., 1999.[5] Schliebusch, O. and Chattopadhyay, A. and Kammler, D. and Ascheid,D. and Leupers, R. and Meyr, H. and Kogel, T., “A Framework forAutomated and Optimized ASIP Implementation Supporting MultipleHardware Description Languages,” in ASP-DAC, Shanghai, China, Jan2005.[6] R. Blahut, Fast Algorithms for Digital Signal Processing. Reading,MS: Addison-Wesley Publishing Company, 1985.[7] B. M. Baas, “A low-power, high-performance, 1024-point fft processor,”in IEEE Journal of Solid-State Circuit, vol. 34, no. 3, 1999, pp. 380–387.[8] Ishebabi, H., Kammler, D., Ascheid, G., Meyr, H., Nicola, M., Masera,G., Zamboni, M., “FFT processor: a case study in ASIP development,”in IST, Dresden, Germany, June 2005.[9] Ishebabi, H., Kammler, D., Ascheid, G., Meyr, H., Atak, O., Atalar,A., Arikan, E., Nicola, M., Masera, G., Zamboni, M., “DESIGN OFAPPLICATION SPECIFIC PROCESSORS FOR THE CACHED FFTALGORITHM,” in ICASSP, Toulouse, France, May 2006.[10] A. Hartstein and T. R. Puzak, “Optimum power/performance pipelinedepth,” in MICRO 36: Proceedings of the 36th annual IEEE/ACMInternational Symposium on Microarchitecture. Washington, DC, USA:IEEE Computer Society, 2003, p. 117.[11] J. Takala, T. Jarvinen, and H. Sorokin, “Conflict-free parallel memoryaccess scheme for fft processors,” in Proceedings of the 2003 Interna-tional Symposium on Circuits and Systems, vol. 4, 2003, pp. IV–524 –IV–527.[12] Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, “A 1-gs/s fft/ifft processor for uwbapplications,” in IEEE Journal of Solid-State Circuits, vol. 40, no. 8,August 2005, pp. 1726–1735.[13] H. Corporaal, Microprocessor Architectures: From VLIW to Tta. NewYork, NY, USA: John Wiley & Sons, Inc., 1997.View publication stats

An efficient parallelization technique for high throughput FFT-ASIPs

http://repository.bilkent.edu.tr/bitstream/11693/27190/1/An%20efficient%20parallelization%20technique%20for%20high%20throughput%20FFT-ASIPs.pdf

An efficient parallelization technique for high throughput FFT-ASIPs

Abstract

Similar works

Full text

Available Versions

Bilkent University Institutional Repository