Bhattacharyya, T. K.

Brüning, U.

Lemke, F.

Schatral, S.

Som, I.

GSI Repository

Status of CBMnet readout and the prototype ASIC∗S. Schatral1,2, F. Lemke1, I. Som3, T.K. Bhattacharyya3, and U. Bruening11University of Heidelberg, Mannheim, Germany; 2GSI, Darmstadt, Germany; 3Indian Institute of TechnologyKharagpur, Kharagpur, IndiaFront-end read-out statusThe CBMnet protocol is currently present in all stagesof the CBM data acquisition (DAQ) network for the TRDand STS readout. Beside the two FEE ASICs using CBM-net links over HDMI cable, the cores are also integrated inthe Read-Out Controller (ROC), the FLES Interface Board(FLIB) and further FPGA to FPGA interconnects. Forthese links Xilinx Gigabit Transceiver over SFPs are used.A typical setup is depicted in 1. To improve the link stabil-ity under influence of radiation, a reworked CBMnet Ver-sion 3.0 has been developed and implemented, containinga link layer, various physical layer implementations andmore network related building blocks to deliver generallyrequired features in CBM network devices. Implementa-tions have been optimized for FPGA and ASIC use. Thelogic is built in such a way, that a malfunction triggeredby a single event effect is detected and the correspondingfunctional blocks are reset. In this manner, the data acqui-sition over a long time is possible without any interruption.Larger test beam read-outs with up to three SPADICs perROC have been tested in laboratory and under beam. TheFLIB physical layer implementation has been tested inten-sively to work reliable under all conditions. The design canhandle up to eight links now.Figure 1: Read-out with FLIB, Syscore3 and SPADICPrototyping of a readout aggregation ASICA prototype of the readout and aggregation ASIC hasbeen designed together with the Indian Institue of Tech-nology Kharagpur (IITKGP). Therefore, an internship stu-dent from IITKGP was visiting the University of Heidel-berg for half a year in 2014. This was possible because of∗Work supported by GSI, BMBF FAIR-CBM 05P12VHFCEsuccessfully raised additional funding from the HeidelbergCenter South Asia. This mixed-signal ASIC consists of afull-custom 5Gb/s serializer/deserializer, designed by theIITKGP including design elements such as phase-lockedloop, bandgap reference, and clock data recovery, and adigital designed network communication and aggregationpart designed by the computer architecture group of theUniversity of Heidelberg.In addition, there are test structures and an I2C readoutintegrated to ease bring up and monitoring. A specialty ofthis test ASIC is the aggregation of links featuring differ-ent data rates, running with bundles of 500 Mb/s LVDS [1].This enables flexible readout setups of mixed detectors re-spectively readout of various chips. There are 1x, 2x, or4x LVDS connections available enabling up to 2 Gb/s fora front-end connection. The prototype will be able to runin a mixed configuration, e.g. one 1x, two 2x, and one 4x.A prototype structure diagram depicting the link configu-ration possibilities is presented in figure 2. As communi-cation protocol for the prototype, a unified link protocol isused including control messages, data messages, and syn-chronization messages on an identical lane. The design hasbeen successfully simulated, verified, and hardware emula-tions using Spartan 6 FPGAs. The miniASIC mixed-signaldesign has been prepared and simulated together with thecollaboration partners from the IITKGP. The first chancein 2015 for a submission using the TSMC 65nm LP Euro-practice process will be taken.Figure 2: Link connection diagram for HUB ASICReferences[1] S. Schatral, F. Lemke, U. Bruening, ”Design of a determin-istic link initialization mechanism for serial LVDS intercon-nects”, Journal, doi:10.1088/1748-0221/9/03/C03022, VOL.9, No. 03, pages C03022, March 2014.MU-NQM-CBM-08 GSI SCIENTIFIC REPORT 201444 DOI:10.15120/GR-2015-1-MU-NQM-CBM-08

Status of CBMnet readout and the prototype ASIC

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Status of CBMnet readout and the prototype ASIC

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