Grybos, P.

Kasinski, K.

Kleczek, R.

Otfinowski, P.

Szczygiel, R.

GSI Repository

Towards the STSXYTERv2, a silicon strip detector readout chip for the STSK. Kasinski, R. Kleczek, R. Szczygiel, P. Grybos, and P. OtfinowskiAGH University of Science and Technology, Cracow, PolandSTS-XYTER as a 128+2 channel full-size prototype ICdedicated for silicon strip detector readout for the STS wasfabricated in 2013 [1]. Fig. 1. presents the test PCB deve-loped at AGH used for functional verification. It provideson-board 5 separate power domains with dedicated low-noise LDO regulators, ERNI connector for sensor attach-ment, interconnects for test interface, test points and AC-coupled CBMnet interface (HDMI connector). The boardis controlled by SysCore V3 (CBMnet) and NI FPGA (testinterface) cards.Figure 1: Test PCB for the STSXYTER ASIC.The architecture details of the chip and test results werepresented and published in [2]. Detailed tests using siliconsensors (e.g. CBM05) are currently being prepared. Usingthe same setup it was possible to further evaluate the chip.Fig. 2. shows the thermal image of the STS-XYTER chipon the test PCB. The thermal resistance was estimated tobe approx. 52 ◦C/W, but it needs to be verified on the finalFEB board in the environment similar to the final appli-cation as well. The temperature coefficients measured forvarious biasing points of of the ASIC evaluated for ambienttemperatures of 7–85 ◦C are:ADC vdiscr ref = -0.622 mV/◦C,ADC ibias corr = -0.312 mV/◦C,BG iref = +0.154 mV/◦C,ADC vref n = -0.366 mV/◦C,ADC vref p = +0.286 mV/◦C,DISCR bias t = -0.435 mV/◦C.The STSXYTERv2 which will be an evolution of theSTSXYTER prototype ASIC among the small fixes thechanges include:• new concept of the digital back-end (focused on theuse of GBTx chip as a data concentrator), reaching hitbandwidths 9.4–47 MHit/s/chip,• definition of the new communication protocol opti-mized for the conditions and requirements of the CBMexperiment. The preliminary protocol was published[3] and is currently a subject of fine-tuning,• configurable front-end (gain, bandwidth) for possiblesupport of gas detectors (MUCH),• new pad layout supporting quality test with pogo-probes and reduced connectivity required for regularoperation,• testability and temperature stability improvements ofthe in-channel ADC,• further optimization of the analog front-end towardslower noise and better stability.The STS-XYTERv2 ASIC is currently being under de-velopment. It is expected to be taped-out in Q2 of 2015 viaEuropractice services.Figure 2: Thermal imaging of the operating ASIC on thetest board.AcknowledgmentWe would like to thank the colleagues from GSI andWUT Warsaw for the efforts towards verification and spec-ification of the new requirements.References[1] P. Grybos et al., “STS-XYTER - a prototype silicon strip de-tector readout chip for the STS”, CBM Progress Report 2012,Darmstadt 2013, p. 17.[2] K. Kasinski et al., “STS-XYTER, a High Count-Rate Self-Triggering Silicon Strip Detector Readout IC for High Res-olution Time and Energy Measurements”, IEEE NSS/MIC,2014.[3] K. Kasinski, W. Zabolotny, R. Szczygiel, “Interface and pro-tocol development for STS read-out ASIC in the CBM exper-iment at FAIR”, Proc. SPIE 9290, doi: 10.1117/12.2074883.MU-NQM-CBM-28 GSI SCIENTIFIC REPORT 201464 DOI:10.15120/GR-2015-1-MU-NQM-CBM-28

Towards the STSXYTERv2, a silicon strip detector readout chip for the STS

http://repository.gsi.de/record/183835/files/MU-NQM-CBM-28.pdf

Towards the STSXYTERv2, a silicon strip detector readout chip for the STS

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