Byszuk, A.

Guminski, M.

Kasprowicz, G.

Pozniak, K.

Romaniuk, R.

Zabolotny, W.

GSI Repository

Towards the Data Processing Boards for CBM experiment∗W. Zabolotny†1, G. Kasprowicz1, A. Byszuk1, M. Guminski1, K. Pozniak1, and R. Romaniuk11Institute of Electronic Systems, Warsaw University of Technology, Warszawa, PolandThe Data Processing Boards (DPB)[1] are important partof the CBM readout and detector control systems, provid-ing concentration (possibly combined with local prepro-cessing) of readout data, before they are sent to the FirstLevel Event Selector (FLES). Additionally DPBs shouldprovide fast and slow control for the Front End Electronics(FEE), distribute the reference clock, and time-critical in-formation, like synchronization and flow control messagesfrom the Timing and Flow Control system (TFC).To allow testing of different possible implementations oflisted functionalities, the versatile prototyping Open Hard-ware platform - AMC FMC Carrier Kintex (AFCK) [2] wascreated. The first version of AFCK is shown in figure 1.Figure 1: The AFCK board with an FMC card with 4 SFP+cages connected to the FMC2 connector.The AFCK board may be used in an MTCA crate orin stand-alone mode. The board is equipped with theXC7K325T FFG900 FPGA, containing 16 high speedGTX transceivers, which can be connected to 2 FMC slots(4 GTXs to each) or to the RTM connector. Another 8GTXs may be connected to the MTCA backplane ports 0to 11. This solution allows to test different transceiversmounted on FMC boards, without modifying the AFCKboard itself. AFCK is also equipped with flexible clock-ing system allowing it operate with gigabit links of differ-ent speed and also to recover a jitter cleaned clock signalfrom a high speed receiver. The board is also equippedwith 2GB of DDR3 SDRAM which may be used to storethe processed data, but also for debugging purposes. Thoseresources make the AFCK board a suitable platform for de-velopment of data concentration and preprocessing algo-rithms.∗Work partially supported by GSI† wzab@ise.pw.edu.plFirst series of AFCK boards was manufactured and func-tionality tests were performed. High speed communica-tion capabilities were tested with standard IBERT tests pro-vided by Xilinx. Stable 10 Gbps transmission was achievedvia GTXs connected to the FMC1 slot, while 5 Gbps trans-mission was possible via GTXs connected to the FMC2 andRTM (10 Gbps in FMC2 should be achievable in next revi-sion of the board).A few basic IP core blocks, suitable for use in the pro-totype DPB firmware were developed or ported and tested.These include the IPbus[3] core allowing to control boardvia 1 Gbps Ethernet interface and the GBT-FPGA[4] coreused to communicate with GBTx ASICs. The Ethernettransmission of readout data at 10 Gbps rate was testedusing the FADE IP core and protocol[5]. Stable transmis-sion of 4x10 Gbps data streams was achieved using 4 SFP+transceivers plugged in FMC board connected to FMC1.Porting of the White Rabbit[6] IP core to the AFCK boardis currently in progress.Results of tests performed with the AFCK board will beused to design the cost optimized version of DPB proto-type.Verification of the STS-XYTER communication pro-tocol developed in collaboration with GSI and AGH [7]was performed in simulations and in hardware, using theKC705 evaluation board. The IPbus accessible controller,allowing to synchronize communication with the model ofSTS-XYTER (provided by the AGH team) and to controlit, was developed and successfully tested. To achieve that,a dedicated environment for hardware-software cosimula-tion of IPbus connected IP cores was prepared.Verified blocks used in controller will be used for de-velopment of prototype DPB firmware, after porting to theAFCK board.References[1] W. Zabolotny and G. Kasprowicz, “Data processing boardsdesign for CBM experiment”, November 2014, Proc. SPIE,vol. 9290,pp. 929023-929023-11[2] http://www.ohwr.org/projects/afck/wiki[3] https://svnweb.cern.ch/trac/cactus[4] https://espace.cern.ch/GBT-Project/GBT-FPGA/default.aspx[5] http://opencores.org/project,fade ether protocol[6] http://www.ohwr.org/projects/white-rabbit/wiki[7] K. Kasinski and W. Zabolotny and R. Szczygiel, “Interfaceand protocol development for STS read-out ASIC in the CBMexperiment at FAIR”, November 2014, Proc. SPIE, vol. 9290,pp. 929028-929028-10GSI SCIENTIFIC REPORT 2014 MU-NQM-CBM-09DOI:10.15120/GR-2015-1-MU-NQM-CBM-09 45

Towards the Data Processing Boards for CBM experiment

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Towards the Data Processing Boards for CBM experiment

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