Carpenter, J.

Kleipa, V.

Schmidt, C. J.

Simons, C.

Soyk, D.

GSI Repository

A Front-end electronics test board for the CBM Silicon Tracking System∗V.Kleipa1, C. Simons1, D. Soyk1, C.J. Schmidt1, J. Carpenter1, the CBM collaboration1, and theFAIR@GSI RBDL11GSI, Darmstadt, GermanyThe 896 modules of the CBM Silicon Tracking Sys-tem will be equipped with two front-end electronics boards(FEBs) each, carrying per board eight STS-XYTER ASICsthat read out the silicon micro-strip sensors of the mod-ules [1]. The boards will be stacked at the top and bottomlayers of the detector, mounted in a shelf structure that is incontact with a cooling plate to remove the power dissipatedby the electronics. Due to the spatial contstraints there,the board dimensions are restricted to the limited size, asshown in Fig. 1. At the same time, the board has to pro-vide the infrastructure for achieving the full output bandwidth needed to read out the detector. This translates to re-alizing up to 5 LVDS pairs per final ASIC, a high-densitychallenge for the FEB design and prototyping.Figure 1: Rendering of the STS front-end electronics boardcomprising 8 STS-XYTER ASICs arranged in a fixed pat-tern on two double-rows of 4 ASICs each. Power supplysection with LDOs on the right. The small componentsare decoupling capacitors to common and communicationground.For assembly test purposes, a PCB was produced ontowhich 8 STS-XYTERv1 ASICs can be mounted but nothaving any electrical functionality. Only the top and bot-tom layers are covered with a gold layer for test bondingof ASICs and cables. During its layout, it turned out thatonly one of the four readout channels of each ASIC couldbe routed to the digital I/O connector, limited due to theavailable space in between the ASICs. This technologicalproblem is the subject of current work.In order to prepare a test equipment for a complete read-out chain from sensor to GBTx boards, an intermediateFEB board has been designed that is not constrained tothe small dimensions. The PCB, called FEB4, hosts onlyfour ASICs. Its layout is shown in Fig. 2. This PCB com-prises the required power supply LDOs. All I/O channelsof each ASIC are linked to a connector. In addition, therequired high-voltage capacitors (rated 250 V) for bias de-coupling have been added to the differential LVDS con-∗ supported by EU-FP7 HadronPhysics3 and by FAIR@GSI PSP code:1.1.1nections. In Fig. 3(a) the board’s assembly pads for passivedevices are visible. For the devices’ case size, the norm0201[m] had to be chosen in order to fit them between theASICs. This board is currently being used for testing ofthe STS-XYTERv1 chips. One ASIC wire-bonded to theboard is shown in Fig. 3(b).Figure 2: Layout of a front-end board comprising fourread-out ASICs and all outgoing LVDS data lines on asomewhat relaxed geometrical footprint (FEB4).(a) (b)Figure 3: (a) High-density region in between the open-ings for the STS-XYTER ASICs on FEB4, filled with thefull set of LVDS lines, micro-vias and connecting pads forhigh-voltage decoupling capacitors. (b) STS-XYTERv1ASIC installed into FEB4 and wire-bonded to its powersupply, control and outgoing data lines.References[1] V. Kleipa et al., CBM Progress Report 2013 (2014), p. 36GSI SCIENTIFIC REPORT 2014 MU-NQM-CBM-44DOI:10.15120/GR-2015-1-MU-NQM-CBM-44 81

A front-end electronics test board for the CBM Silicon Tracking System

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A front-end electronics test board for the CBM Silicon Tracking System

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