Garcia, C.

Kebschull, U.

GSI Repository

Development of an online feature extraction pre-processing stage for TRDbased on SPADIC 1.0 ∗C. Garcia1 and U. Kebschull11Infrastructure and Computer Systems for Data Processing (IRI), Frankfurt University, Frankfurt/Main, GermanyOne of the main challenges for the data acquisition of theTransition Radiation Detector (TRD) of the CompressedBaryonic Matter experiment (CBM) is to efficiently pro-cess the high data rate produced by the front-end electron-ics operating in a free streaming data acquisition mode. Inthis scenario, the TRD detector is read-out by the front-endmixed-signal SPADIC 1.0 chip [1]. The SPADIC 1.0 de-livers 32 autonomous read-out channels with a large set ofmeta-information attached to the generated messages. Inorder to fulfill the processing requirements for the TRD, afeature extraction online pre-processing stage has been pro-posed [2]. The aim of the feature extraction is to do an on-line pre-processing of the front-end electronics data, in or-der to reduce it by means of parameter extraction and clus-tering. The Feature Extraction pre-processing stage wouldbe integrated within the functionality of the Data Process-ing Board (DPB) [3].As seen in Figure 1, the internal processing logic ofthe Feature Extraction firmware would allow to instantiatemultiple “link processors” in parallel in order to handle thedata from different data-input optical links. However, themaximum number of link processors would be constrainedby the FPGA resources available.The internal architecture of the feature extraction coreis based on the following processing stages: first, a mes-sage interpreter module decodes the incoming SPADIC 1.0event words wrapped around the CBMnet 2.0 headers anddelivers the full timebin RAW data, as well as useful meta-data attached to the hit message (e.g. timestamp, channelid, group id, hit type, etc). This decoded data is then han-dled by the double-hit detection logic. The double-hit logicworks in two configurable modes: first, in conjunction tothe double-hit detection logic implemented in the SPADIC1.0 chip and second, as a stand-alone detection logic. Inthe first case, the double-hit logic compares the hit-messageflags set by the SPADIC 1.0 that tell whether a double-hitwas detected or not. In the second case, as a stand-alonedetection mode, the logic compares the signal charge withdifferent virtual thresholds at different timebin positions. Aparallel running module finds the peaks and valleys in thesignal evolution. These information is used by a later logicthat splits the message between two maxima, when a valleyhas been found.The second processing stage consists mostly of two par-allel processes, a total charge integrator (Qtot) and a tem-poral center of gravity calculator (COG). The Qtot moduledelivers an amplitude vs. time integration from a region ofinterest or from all the timebins included in the event. On∗Work supported by BMBF No. 05P12RFFCM.the other hand, the COG calculates the center of gravityof the signal in time direction. In order to save FPGA re-sources, the feature extraction can be configured to use onlyone of the before mentioned cores. Further beamtest analy-sis will show which processing module gives better resultsfor the event reconstruction. A final processing stage iscalled cluster finder and processor. This module finds clus-ters from events that share similar characteristics, e.g. con-tiguous fired pads, events with a timestamp that falls withina certain threshold and also by comparing the neighbor trig-ger matrix flags generated by the SPADIC 1.0. Finally, af-ter a cluster has been completed, the data from each eventthat belongs to the found cluster is processed by a Centerof Gravity (COG) algorithm that provides a temporal res-olution of the hit position within the found cluster. In theend, the event building logic wraps the hit-message intoCBMnet2.0 containers in order to be shipped to later DPBprocessing stages.Figure 1: Block diagram of the internal architecture of thefeature extraction core.Currently, most functionality of the Feature Extractionfirmware has been developed and is under continuous test-ing in a laboratory setup. In 2014, a TRD beamtest willbe performed in order to test and provide consistent resultsabout performance and FPGA resource consumption.References[1] T. Armbruster et al., “SPADIC 1.0 a self-triggered ampli-fier/digitizer ASIC for the CBM-TRD”,CBM Progress Re-port 2012[2] C. Garcia et al., “Beam test results of the CBM-TRD featureextraction using SPADIC v1.0”,CBM Progress Report 2012[3] J. Gebelein et al., “SysCore3 A universal Read-Out Con-troller and Data Processing Board”,CBM Progress Report2012GSI SCIENTIFIC REPORT 2013 NQM-CBM-31doi:10.15120/GR-2014-1-NQM-CBM-31 47

Development of an online feature extraction pre-processing stage for  TRD based on SPADIC 1.0

http://repository.gsi.de/record/67777/files/NQM-CBM-31.pdf

Development of an online feature extraction pre-processing stage for TRD based on SPADIC 1.0

Abstract

Similar works

Full text

Available Versions

GSI Repository