Groß, K.

Klingbeil, H.

Kumm, M.

Lens, D.

Möller, K.

Zipf, P.

GSI Repository

FPGA Based Tunable Digital Filtering for Closed Loop RF Control inSynchrotrons∗Konrad Mo¨ller†1, Martin Kumm1, Peter Zipf 1, Kerstin Groß2, Dieter Lens2, and Harald Klingbeil 2,31Digital Technology Group, University of Kassel; 2Accelerator Technology, Technische Universita¨t Darmstadt; 3GSIIntroductionThe longitudinal feedback system for the FAIR acceler-ator SIS100 will rely on digital filters for damping longi-tudinal bunch oscillations. Filters with a minimum timedelay are needed, thus an implementation on a field pro-grammable gate array (FPGA) is necessary. In addition,the filter implementation has to be flexible enough for areal-time adaptation of the filter coefficients during the ac-celeration ramp. This will enable the tuning of the longi-tudinal feedback with respect to the synchrotron frequencyand other relevant parameters. The filter length will be con-siderably longer than the currently used three-tap filter ofthe beam phase feedback [1], offering more degrees of free-dom.FilterIn order to achieve a constant group delay an finite im-pulse response (FIR) filter was chosen. The fundamentaloperation of an N -tap FIR filter is the inner product of avector containing N time shifted scalars of the filter inputx with a vector c consisting of the filter coefficients. Ina tunable filter design c has to be adapted to the currentRF frequency. The adaption of the filter coefficients canbe achieved by using a look-up table (LUT) based multi-plication scheme on the FPGA. Here, a general purposemultiplier is replaced by a constant coefficient multiplierconsisting of LUTs containing partial products followedby bit shifts and adders to calculate the final result. Thisconcept, introduced in [2] was customized with reconfig-urable LUTs (content can be changed during run-time) onrecent FPGAs [3]. A reconfiguration can be performed in16 clock cycles which corresponds to 160 ns in the currentimplementation. This is fast enough to tune the filter char-acteristics between the calculation of two filter outputs andthus leading to glitch-free switching.The block diagram of the resulting dynamically recon-figurable FIR filtering is shown in Figure 1. Our imple-mentation realizes a filter with up to N = 64 non-zero-taps.Between these taps a tunable number L of virtual zero-tapsare inserted to tune the bandpass characteristics of the fil-ter. In addition to this tuning possibility, a larger range ofinput samples is considered which allows filtering of lowerfrequency components as well.∗Work supported by BMBF, contract No. 05P12RKRBE.† konrad.moeller@uni-kassel.deFigure 1: Dynamically reconfigurable FIR filter using re-configurable LUT multiplication (in dashed lines)Figure 2: Simulation: open loop (black), closed loop (blue)Simulation and OutlookAs an example, the closed-loop performance of an FIRfilter used in a longitudinal beam phase feedback loop forSIS18 is shown in Fig. 2. In this nonlinear tracking simu-lation, Ar18+ with a kinetic energy of 11.4MeV/u is as-sumed as ion species. At t = 2.32ms, dipole oscillationsare intentionally induced by an RF phase shift. The ampli-tude of the gap voltage is 1 kV, resulting in a synchrotronfrequency of 740Hz. In this case, the filter was designedas a highpass filter with N = 15 and L = 30.In future several new filter designs will be possible dueto the large number of taps. Further studies will also dealwith the optimization of the filter design.References[1] H. Klingbeil, B. Zipfel, M. Kumm, and P. Moritz. A Digi-tal Beam-Phase Control System for Heavy-Ion Synchrotrons.IEEE Trans. Nucl. Sci., pages 2604–2610, 2007.[2] K. D. Chapman. Fast integer multiplier fit in FPGA’s. EDNAccess, pages 79–80, 1994.[3] M. Kumm, K. Moeller, and P. Zipf. Dynamically reconfig-urable FIR filter architectures with fast reconfiguration. Re-configurable and Communication-Centric Systems-on-Chip(ReCoSoC), 8th International Workshop on, 2013.GSI SCIENTIFIC REPORT 2013 FG-SIS100-08doi:10.15120/GR-2014-1-FG-SIS100-08 FAIR@GSI 331 FG-SIS100-08 GSI SCIENTIFIC REPORT 2013332 doi:10.15120/GR-2014-1-FG-SIS100-08

FPGA Based Tunable Digital Filtering for Closed Loop RF Control in Synchrotrons

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