Grybos, P.

Kasinski, K.

Kleczek, R.

Otfinowski, P.

Szczygiel, R.

GSI Repository

STS-XYTER a prototype silicon strip detector readout chip for the STSP. Grybos1, K. Kasinski1, R. Kleczek1, P. Otfinowski1, and R. Szczygiel∗11AGH-UST, Krakow, PolandThe STS-XYTER prototype readout ASIC for the CBMSTS detector was designed in 2012. It is a full size proto-type dedicated for signal detection from the double-sidedmicrostrip sensors in the CBM environment. The self-triggering ASIC provides both timing and energy infor-mation for each incoming signal in its channels.The chip includes 128 channels. The input current pulsefrom the detector is processed by the charge sensitive am-plifier (CSA). The signal path is then split into a fast anda slow one (Fig. 1). The fast path includes a fast shaperwith a typical shaping time of 30 ns, a discriminator and atimestamp latch. It is optimized to provide good timing res-olution (<10 ns). The slow path consists of a slow shaperwith the typical shaping time of 80 ns, a 5-bit flash ADCand a digital peak detecting logic. It is optimized for energymeasurement and noise performance.Figure 1: Block scheme of the STS-XYTER chip.For a particle hit, each channel provides the timestampand the ADC value corresponding to the deposited charge.Data from the channels are read out using a token-ringstructure, controlled by a readout controller. The gathereddata are sent out via up to four 500 Mbit/s LVDS serialdata links. The data transfer to and from the chip is imple-mented according to the CBMnet protocol description. TheHDL code of the CBMnet-related digital part was providedby ZITI, UNI-Heidelberg [1]. A simplified I2C interfaceallows to configure the chip without protocol overhead fortest purposes. A summary of the most important parame-ters can be found in table 1.The essential new feature compared to the n-XYTER ar-chitecture is an effective two level discriminator scheme.The discriminator in the fast signal lane triggers the latchof the timestamp at high timing resolution. Because of thehigher bandwidth of the fast lane, the noise level and thusthe noise related trigger rate is comparatively high in such aself-triggered system if the discriminator level is kept low.The noise-related trigger rate is determined by the Rice for-mula. If the discrimination level is kept below 3σ, noise-related hits would swamp data channels and create deadtime, while if kept too high, the essential low level hits∗ robert.szczygiel@agh.edu.plTable 1: Design parameters of ASIC.Number of channels 128 + 2 testPad / channel pitch 58 μmInput signal polarity Positive and negativeAccepted input leakage current 10 nAENC @ 30 pF det. capacitance 900 e-Voltage gain in slow path 25 mV/fCVoltage gain in fast path 71 mV/fCADC range 16 fCInput clock frequency 250 MHzTimestamp resolution <10nsPower consumption <10 mV/channelOperating temperature range 0◦C < T < 40◦CDigital interface standard 4x 500 Mbit/s LVDSwould remain undetected. The two level trigger schemeemployed in the STS-XYTER adds a veto to the transmis-sion of data in case the flash ADC has generated ”zero”.The discrimination level of the LSB is controlled by aninternal register and effectively serves as a secondary dis-criminator that is exposed to the low bandwidth, low noiseenergy signal. This strategy makes the Rice formula appli-cable to the signal of the energy channel while keeping thehigh time resolution achieved from triggering on the fasttiming channel.Figure 2: STS-XYTER ASIC layout.The ASIC was designed using the UMC 180 nm processand was sent for manufacturing in October 2012. The diesize is 6.5 mm x 10 mm (Fig. 2). A detector is to be con-nected via a Kapton cable attached to the ASIC using tabbonding. The power supply, biasing and digital interfacepads are designed for wire-bonding. Particularly sensitiveelements of the chip were made radiation hard.References[1] F. Lemke, D. Slogsnat, N. Burkhardt, U. Bruening, “A Uni-fied DAQ Interconnection Network with Precise Time Syn-chronization”, IEEE Transactions on Nuclear Science (TNS),Vol. 57, No. 2, 2010.GSI SCIENTIFIC REPORT 2012 PHN-NQM-EXP-2251

STS-XYTER a prototype silicon strip detector readout chip for the STS

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STS-XYTER a prototype silicon strip detector readout chip for the STS

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