de Cuveland, J.

Hutter, D.

Lindenstruth, V.

GSI Repository

Status of CBM First-level Event Selector Prototype Developments∗J. de Cuveland1, D. Hutter1, and V. Lindenstruth11FIAS Frankfurt Institute for Advanced Studies, Goethe-Universität Frankfurt am Main, GermanyThe First-level Event Selector (FLES) is the centralevent selection system in the CBM experiment. Its task isto select data for storage based on online analyses includinga complete event reconstruction. To do so, the FLES time-slice building has to combine data from all input links totime intervals and distribute them via a high-performancenetwork to the compute nodes. Data rates at this point areexpected to exceeds 1 TByte/s. It has proven practical touse an InfiniBand network for data transfer between theFLES nodes. Even so, further investigations are needed todesign the final system and develop the required softwarealgorithms.Micro-FLES ClusterTo provide a small scale, highly customizable platformfor these studies, the Micro-FLES cluster was installed atGSI (see Fig. 1). Eight identical compute nodes provide atotal of 192 logic cores and 512GB memory. While con-suming only 1U of installation space, the nodes still pro-vide PCIe 3.0 expansion slots for up to 2 FLES InterfaceBoards (FLIB) and 3 GPU cards. This allows additionaltests of the full data transport chain and reconstruction al-gorithms in the future. In addition to the compute nodes,one head node provides infrastructure services such as stor-age and boot images. Although there is local storage in thecompute nodes for test purposes, it is currently not used foroperating the cluster.For timeslice building the cluster is equipped with astate-of-the-art InfiniBand FDR network. Each node of-fers two 56Gbit/s 4x FDR ports currently connected to onecore switch. The availability of two ports per node easilyallows the study of more complex network topologies.Complementarily, the development of a timeslice-building test software based on InfiniBand Verbs hasstarted. Especially questions regarding data structures,buffer management, and network scheduling are addressed.Preliminary tests using the same data structures as intendedfor the final setup have shown promising results.FLES Interface Board (FLIB)In the process of upgrading the CBMnet-based prototyperead-out chain, a replacement for the currently used PC in-terface board (namely the ABB) is needed. For this pur-pose the FLIB prototype board derived from the ALICEC-RORC [1] has been chosen. Based on a Xilinx Virtex-6FPGA, it features an eight-lane PCIe Gen 2 interface, up to12 optical links and two DDR3 memory sockets.∗Work supported by BMBF (05P12RFFCP) and HIC for FAIRFigure 1: TheMicro-FLES cluster installed at GSIMCindexingDMA channelMCsDMA Mux. . .per channelPCIe MC AddrMC gen. . .ADDRMC 0ADDRMC 1HDR MC 0HDR MC 1CONTENT MC 0. . .CONTENT MC 1DTM packetizerpacked DTMsCBMnetDTMsCONTENT DTM 0. . .CONTENT DTM 1CONTENT DTM 2HDR DTM 0HDRDTM1CONTENT DTM 0. . .CONTENT DTM 1CONTENT DTM 2HDR DTM 2Figure 2: Schematic view of the FLIB read-out data pathIn contrast to the final system, early prototype setups willnot support the creation of microslice containers (MC) (asdescribed in [2]). Hence, a firmware was developed that iscapable of reading out raw CBMnet messages as deliveredfrom the CBM front-end electronics.The corresponding data path is shown in Figure 2. In thefirst step, incoming CBMnet messages are preprocessed inhardware to facilitate subsequent software processing. Af-ter preprocessing, a separate module packages the incom-ing data into simplified MCs, whose reduced data contentrequirements (in comparison to ordinary MCs) support notyet fully synchronized detector electronics. Finally, an ad-dress index table is created and MCs are written to the PChost memory via the PCIe interface. The chosen partition-ing of the design and the creation of simplified MCs en-ables reuse of developed hardware and software compo-nents when migrating to a fully microslice-based read-outchain.References[1] H. Engel et al, "ALICE C-RORC as CBM FLES InterfaceBoard Prototype", this report[2] J. de Cuveland et al, "CBM First-level Event SelectorDataflow Architecture and Microslice Concept", GSI Sci. Re-port 2011, PHN-NQM-CBM-41, p 63.PHN-NQM-EXP-46 GSI SCIENTIFIC REPORT 201276

Status of CBM First-level Event Selector Prototype Developments

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Status of CBM First-level Event Selector Prototype Developments

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