Complexity in the digital systems integration rises from the heterogeneity of the components integrated in a chip. The simulation or code generation of such systems require to validate methodologies, platforms and technologies to support integration, verification and programming, of complex systems composed of heterogeneous virtual components. Several formalisms are needed according to their applicability in order to propose a framework of formal specification. The unification of these formalisms leads to visually model intensive signal processing applications for embedded systems. A part of this methodology has come down from the Array-OL language. An application is represented by a graph of dependences between tasks and arrays. Thanks to the data-parallel paradigm, a task may iterate the same code on different patterns which tile its depending arrays. The visual notation we propose uses a UML 2.0 standard proposal. This allows usage of existing UML 2.0 tools to model an application. A UML profile dedicated to Intensive Signal Processing with a strong semantics allows automatic code generation, automatic mapping on SoC architectures for early validation at the higher level of specification
