RR 2004-18, ENS-Lyon, 24 pagesWe present new results concerning the integration of high level designed ips into a complete System on Chip. We first introduce a new compu- tation model that can be used for cycle accurate simulation of register transfer level synthesized hardware. Then we provide simulation of a SoC integrating a data-flow ip synthesized with MMAlpha and the So- cLib cycle accurate simulation environment. This integration also vali- dates an efficient generic interface mechanism for data-flow ips
