A quaternary current mode bus driver and receiver circuits.

Abstract

Cheung, Cheuk Kit.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references.Abstract also in Chinese.Abstract --- p.1摘要 --- p.2Acknowledgements --- p.3Table of Contents --- p.4List of Figures --- p.9Chapter 1. --- Introduction --- p.12Chapter 1.1. --- Research Motivation --- p.12Chapter 1.1.1. --- Global and Intermediate Interconnects --- p.12Chapter 1.1.2. --- Constraints of Repeater Insertion Techniques --- p.13Chapter 1.2. --- Research Objective --- p.13Chapter 1.3. --- Reference --- p.14Chapter 2. --- Voltage Mode and Current Mode Circuits --- p.16Chapter 2.1. --- Introduction --- p.16Chapter 2.2. --- Voltage Mode Circuit --- p.16Chapter 2.3. --- Current Mode Circuit --- p.18Chapter 2.4. --- Power Consumption --- p.19Chapter 2.5. --- Latency --- p.20Chapter 2.6. --- Summary --- p.20Chapter 3. --- Transmitter Design --- p.22Chapter 3.1. --- Introduction --- p.22Chapter 3.2. --- Multi-level Signaling --- p.22Chapter 3.3. --- Gated Current Mirror --- p.23Chapter 3.4. --- Power Consumption --- p.24Chapter 3.5. --- Summary --- p.24Chapter 3.6. --- Reference --- p.25Chapter 4. --- Receiver Design --- p.26Chapter 4.1. --- Introduction --- p.26Chapter 4.2. --- Conventional Latched-typed Sense Amplifier --- p.27Chapter 4.3. --- Sense Amplifier with Isolated Differential Pair --- p.29Chapter 4.4. --- "Power Consumption, Latency and Kick-back Noise Comparison between Different Designs" --- p.30Chapter 4.4.1. --- Comparison on Power Consumption --- p.30Chapter 4.4.2. --- Comparison on Latency --- p.31Chapter 4.4.3. --- Comparison on Kick-back Noise --- p.33Chapter 4.5. --- Summary --- p.34Chapter 4.6. --- Reference --- p.34Chapter 5. --- Inverter Chain --- p.36Chapter 5.1. --- Introduction --- p.36Chapter 5.2. --- Inverter Chain Based --- p.36Chapter 5.3. --- Summary --- p.38Chapter 5.4. --- References --- p.38Chapter 6. --- Layout Techniques --- p.39Chapter 6.1. --- Introduction --- p.39Chapter 6.2. --- Two-Dimensional Common Centroid Layout Technique --- p.39Chapter 6.3. --- Dummy Devices --- p.40Chapter 6.4. --- Summary --- p.42Chapter 6.5. --- References --- p.42Chapter 7. --- Simulation Results --- p.43Chapter 7.1. --- Introduction --- p.43Chapter 7.2. --- Simulation of Different Aspect Ratios of Differential Pair --- p.43Chapter 7.3. --- System Level Simulation with Different Sense-amplifiers --- p.46Chapter 7.4. --- System Level Simulation at Different Data Rate --- p.47Chapter 7.5. --- Summary --- p.49Chapter 8. --- Measurement Results --- p.50Chapter 8.1. --- Introduction --- p.50Chapter 8.2. --- Experimental Setup --- p.50Chapter 8.2.1. --- Testing Chips --- p.50Chapter 8.2.2. --- Equipments Setup --- p.52Chapter 8.3. --- Measurement Results --- p.53Chapter 8.4. --- Summary --- p.56Chapter 9. --- Conclusion --- p.57Chapter 9.1. --- Author´ةs Contributions --- p.57Chapter 9.2. --- Future Works --- p.58Chapter 10. --- Appendix --- p.5