Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling

Abstract

Power consumption is nowadays a critical design constraint for circuits and systems. To guide efficiently early choices in the design flow, high-level estimations must be available. In order to address the different abstraction levels and the various targets, a global methodology is proposed here to elaborate suitable models. These models are obtained through the Functional Level Power Analysis, first developed for processors and then extended to memory and FPGA. This paper is a synthesis of various works, conducted through several collaborations; some resulting models are given to illustrate the parametric approach at the system, algorithmic and architectural levels for either hardware or software component. From these models, optimizations can be deducted from the sensitivity metric and finally an estimation approach for System-On-Chip is described