An FPGA Configuration Stream Architecture Supporting Seamless Hardware Accelerator Migration

Abstract

International audienceMost of the available commercial Field Programmable Gate Arrays (FPGA) use an addressable memory organized around an array of N-bit words of Static RAM (SRAM) cells. Such configuration memory is traditionally programmed by writing, to each word, the corresponding bit-stream data at runtime. In the growing domain of Dynamic Partial Reconfiguration, this leads to long reconfiguration time of dynamic regions. We propose a novel approach to task relocation in an FPGA-based reconfigurable fabric, allowing for offline design, routing and unfinalized placement of hardware IPs and dynamic placement of the corresponding bit-streams at runtime