In this paper, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried In&lt;sub&gt;0.53&lt;/sub&gt;Ga&lt;sub&gt;0.47&lt;/sub&gt;As channel devices employing an Atomic Layer Deposited (ALD) Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure.

Peak electron mobilities of 4300 cm&lt;sup&gt;2&lt;/sup&gt;/V·s and 6600 cm&lt;sup&gt;2&lt;/sup&gt;/V·s at a carrier density of 3×1012 cm&lt;sup&gt;-2&lt;/sup&gt; for the surface and buried channel structures respectively were determined. In contrast to similarly scaled inversion-channel devices, we find that mobility in surface channel flatband structures does not drop rapidly with electron density, but rather high mobility is maintained up to carrier concentrations around 4x10&lt;sup&gt;12&lt;/sup&gt; cm&lt;sup&gt;-2&lt;/sup&gt; before slowly dropping to around 2000 cm&lt;sup&gt;2&lt;/sup&gt;/V·s at 1x10M&lt;sup&gt;13&lt;/sup&gt; cm&lt;sup&gt;-2&lt;/sup&gt;. We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for future low power, highly scaled CM

Ahn, J.

Asenova, A.

Bentley, S.

Holland, M.

Ignatova, O.

Li, X.

Macintyre, D.

McIntyre, P.C.

Paterson, G.

Shin, B.

Thayne, I.

Thoms, S.

Zhou, H.

IEEE Electron Device Letters

English

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Bentley, S. et al. (2011) Electron mobility in surface- and buried- channel flatband In0.53Ga0.47As MOSFETs with ALD Al2O3 gate dielectric. IEEE Electron Device Letters, 32 (4). pp. 494-496. ISSN 0741-3106 http://eprints.gla.ac.uk/52717/ Deposited on: 10 June 2011 Enlighten – Research publications by members of the University of Glasgow http://eprints.gla.ac.uk > EDL-2010-12-2162 < 1 Abstract—In this paper, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried In0.53Ga0.47As channel devices employing an Atomic Layer Deposited (ALD) Al2O3 gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm2/V·s and 6600 cm2/V·s at a carrier density of 3×1012 cm-2 for the surface and buried channel structures respectively were determined. In contrast to similarly scaled inversion-channel devices, we find that mobility in surface channel flatband structures does not drop rapidly with electron density, but rather high mobility is maintained up to carrier concentrations around 4x1012 cm-2 before slowly dropping to around 2000 cm2/V·s at 1x1013 cm-2. We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for future low power, highly scaled CMOS. Index Terms— InGaAs, MOSFET, ALD, electron mobility I. INTRODUCTION HE continual requirements of the CMOS International Technology Roadmap for Semiconductors [1] for increased performance and density have led to the introduction of myriad non-classical performance boosters such as high-κ metal gate stacks and strained channels, and it is expected that continued EOT scaling will require the SiO2 interfacial layer to be eliminated [2]. As a consequence, the III-V/high-κ interface has attracted significant interest, initially due to the potential of III-V structures for high electron velocity, evidenced by the high performance achieved in scaled III-V HEMTs [3]. It is now anticipated that III-V MOSFETs may allow higher drive Manuscript received December 24, 2010. This work was supported in part by the UK Engineering and Physical Sciences Research Council under Grant EP/F002610/1 and the Semiconductor Research Corporation via the Non-classical CMOS Research Center. S. Bentley, M. Holland, X. Li, G. Paterson, H. Zhou, O. Ignatova, D. Macintyre, S. Thoms, A. Asenov and I.G. Thayne are with the Nanoelectronics Research Centre, School of Engineering, University of Glasgow, Glasgow, UK (e-mail: steven.bentley@glasgow.ac.uk). B. Shin was with the Department of Materials Science and Engineering, Stanford University, Stanford, CA 94305 USA. He is now at IBM T.J. Watson Research Center, Yorktown Heights, NY 10598 USA. J. Ahn and P.C. McIntyre are with the Department of Materials Science and Engineering, Stanford University, Stanford, CA 94305 USA (e-mail: pcm1@stanford.edu). current and transconductance than silicon at its low power scaling limit [4], making them an attractive n-channel solution. Much recent work [5-8] has focused on the development of inversion-mode III-V nMOSFETs. Such devices, though eminently silicon-like, have not demonstrated the superior transport potential of a heterostructure quantum well, enabled by the epitaxial techniques used in III-V fabrication. Conversely, much work has also been undertaken on the development of buried-channel quantum well nMOSFETs, but their scaling potential remains unclear as a consequence of the inclusion of wide-bandgap layers above the channel [4, 6]. In this letter, we present highly-scaled surface and buried channel flatband nMOSFET structures which maintain mobilities up to 4300 and 6600 cm2/V·s respectively, at electron densities relevant for device operation. II. EXPERIMENT For the buried channel devices, the following layers were grown sequentially by molecular beam epitaxy on 2” semi-insulating (100) InP substrates: a 400 nm In0.52Al0.48As buffer, silicon δ-doping with a density of 3×1012 cm-2, a 4 nm In0.52Al0.48As spacer, a 10 nm lattice-matched In0.53Ga0.47As channel, a 2 nm In0.52Al0.48As barrier and a 2 nm In0.53Ga0.47As cap. In the case of the surface channel structure, the upper two layers were omitted. Apart from the δ-doping planes, all layers were nominally undoped. The wafers were then capped in situ in the MBE tool using an amorphous arsenic cap to protect the surface from oxidation, loaded into an ALD chamber and the arsenic cap desorbed in situ [10]. 60 cycles of Al2O3 (approximately 6 nm) were then grown at 270ºC using TMA and H2O precursors in a TMA-first ALD process [11]. MOSFETs were fabricated in two lithographic steps using a wrap-around gate, obviating the need for device isolation [12]. First, a platinum/gold gate was defined by electron beam lithography (EBL) and liftoff. Non-self-aligned ohmic contacts were then defined by EBL, selective wet etching of the Al2O3 in dilute KOH and electron beam evaporation of Ni/Ge/Au-based ohmic contacts. The contacts were alloyed in a 60s RTA process in a nitrogen atmosphere at 280ºC. MOS capacitors were simultaneously defined adjacent to the MOSFETs. The wafers underwent no additional post-Electron Mobility in Surface and Buried Channel Flatband In0.53Ga0.47As MOSFETs with ALD Al2O3 Gate Dielectric. Steven J. Bentley, Member, IEEE, Martin Holland, Xu Li, Gary W. Paterson, Haiping Zhou, Olesya Ignatova, Douglas Macintyre, Stephen Thoms, Asen Asenov, Senior Member, IEEE, Byungha Shin, Jaesoo Ahn, Paul C. McIntyre and Iain G. Thayne T > EDL-2010-12-2162 < 2 deposition forming gas processing, which has been shown to reduce the interface state density (Dit) [13]. Fig. 1 a) Log Id,gm(Vgs) measurements of 20 µm gate length devices at Vd=50 mV and 1 V and matched gate overdrive. b) C-V measurements of 100 µm diameter dots used for mobility extraction. III. RESULTS AND DISCUSSION Typical log Id,gm(Vgs) characteristics of surface and buried channel 20 µm gate length devices at Vd = 50 mV and 1 V are shown in Fig. 1. The surface and buried channel devices feature threshold voltages of -0.13 V and -0.87 V respectively. For comparison, transfer characteristics are shown for matched gate overdrive. At 2 V gate overdrive and Vd = 1 V, Id was 130 µA/µm and 195 µA/µm for the surface and buried channel devices respectively. At Vd = 50 mV, the subthreshold swings of the surface and buried channel devices were 195 mV/dec and 430 mV/dec respectively. Calculating CET at threshold, these equate to approximate Dit figures of 7.3×1012 cm-2 and 1.8×1013 cm-2 respectively. We believe this difference may be due to the specific bandgap energies and therefore trap distributions swept by the Fermi level at the oxide/semiconductor interface in the two device structures as the gate voltage is varied. Another notable feature in Fig. 1a is the "double-peak" in the gm(Vg) characteristic of the buried channel device, which we believe reflects charge transfer from the channel to the upper semiconductor layers at higher gate bias. Multi-frequency C-V measurements of 100 µm diameter MOS capacitors are also included in Fig. 1. The measured maximum capacitance scales with CET as expected when considering the additional semiconductor layers in the buried structure. The surface channel devices featured on-resistances of 3030 Ω·µm and total access resistance of 1140 Ω·µm per side. As a consequence of lower sheet resistance, the buried channel devices had figures of 1160 Ω·µm and 540 Ω·µm respectively. Effective mobility was extracted as a function of the channel electron concentration using a combination of I-V and C-V measurements. The wrap-around gate process precludes conventional split-CV characterization, hence the mobility is determined by extracting the gate voltage dependent channel carrier density from C-Vg capacitor measurements at 1 MHz and low-field Ids-Vgs from an adjacent MOSFET at Vd = 50 mV [12]. The resultant room temperature mobility/carrier concentration data are shown in Fig. 2. Many data, e.g. [5], published for III-V inversion channel mobility include a “correction” for the effect of the interface state density, using simulated capacitance data. It should be noted that we employ no such correction. Also shown for comparison are mobility data from various inversion channel In0.53Ga0.47As MOSFETs [6-8] and Hall data extracted from Van der Pauw structures for both flatband designs. Fig. 2 Mobility of surface and buried channel flatband devices as compared to various ALD/In0.53Ga0.47As inversion mode devices (dashed) from [6-8] and a fully-undoped surface channel quantum well [9]. In contrast to other devices, surface channel flatband devices exhibit high mobility over the complete electron density range, similar to buried channel devices. The surface channel flatband design exhibits peak mobility of around 4300 cm2/V·s: significantly lower than the peak mobility of 6600 cm2/V·s extracted from the buried channel wafer, which may indicate increased roughness at the ALD oxide/channel interface over that of the epitaxial barrier/channel interface in buried channel devices. Extracted Hall mobilities on both structures are notably higher than those from transistor measurements, which may a result of the different extraction techniques, and particularly the contribution of oxide charge to the capacitance. In both cases, however, the carrier concentration dependence of the mobility is notably different from the characteristics of inversion channel In0.53Ga0.47As devices, for which the mobility peaks at low electron concentration, then rapidly decreases with increasing density [6-8]. The mobility from our surface channel devices, in contrast, peaks at around 4300 cm2/V·s before decreasing with increasing electron density to around 2000 cm2/V·s at a density of 1×1013 cm-2: behavior very similar to our buried channel devices. The only mobility data for surface channel quantum well devices in literature [9] are also included. Although otherwise similar, these devices do not feature delta doping, and their mobility, whilst higher than in an inversion channel, is relatively low and decays rapidly with increasing electron density in comparison to the data reported in this letter. The superior mobility of our devices may be explained by the use of both an undoped channel and quantum confinement in the presence of delta doping on the backside of the channel. To explain the high mobility, numerical simulations of the electron populations of our surface channel flatband structure and a theoretical inversion mode device were undertaken, and are found in Fig. 3. Both configurations employ a lattice-matched 10 nm In0.53Ga0.47As channel on an In0.52Al0.48As -1 0 1 21E-41E-30.010.1110100 Vg-Vt (V) I d(µA/µm)024681012 Surface BuriedVds=50 mVVds=1 Vg m (µS/µm)Vds=50 mV(a)-3 -2 -1 0 1 20100200300400500600700800900Vgs (V)C (nF/cm2 )Surface 1 kHz 10 kHz 100 kHz 1 MHzBuried(b)Figure 1: Field-depen ent transport .10 2x1012 4x1012 6x1012 8x1012 1x101302000400060008000Surface channel, this workSurface channel Hall, this workBuried channel, this workBuried channel Hall, this workSematech inversion [6]IMEC inversion [7]Penn State inversion [8]UT surface channel [9]Sheet electron density (cm-2)Mobility (cm2 /V·s)> EDL-2010-12-2162 < 3 spacer to provide heterostructure confinement. In the inversion-channel device, the channel is p-doped at 1×1017 cm-3. The electron distributions in these two devices are compared for matched electron density in each case. The mobility of the flatband device below threshold is likely limited by remote impurity scattering from the doping. Above threshold (Fig. 3a), the channel forms towards the back of the quantum well as a consequence of the delta doping, and a high electron density accumulates here initially, screening the dopant. In this region, the mobility is therefore largely unaffected by the oxide interface roughness scattering and dominated rather by that at the heterostructure interface. As the gate bias is increased, electrons populate the whole channel (Fig. 3b), becoming subject to roughness scattering from both interfaces. Even at high bias (Fig. 3c), however, a significant fraction of the electrons remain at the rear of the channel, where mobility is at its maximum. In contrast, as the inversion mode device switches on, the channel is formed close to the oxide interface. The p-doped depletion layer exerts a large vertical electric field on the inversion layer charge, which encounters strong oxide interface roughness scattering. The vertical electric field continuously increases with the increase of the channel carrier concentration as gate bias is increased. Consequently, the electron population is always subject to increased interface roughness scattering at the immediate oxide interface as compared to the flatband device. Fig. 3 1-dimensional Poisson-Schrödinger simulations of electron populations of a surface channel flatband device (solid line) and an inversion mode device comprising a 10 nm In0.53Ga0.47As channel (dashed line), compared for matched electron densities. In each case, the flatband device electron density is less constrained to the oxide interface than in the inversion-mode device. We believe that remote interface roughness and coulomb scattering from the oxide interface limit the mobility in our surface channel structure. In the buried channel, decreased proximity of the charge to the oxide interface further increases mobility. As a result, the vertical field dependence of the interface roughness scattering from the rear spacer interface becomes clearly identifiable at densities of 1-4×1012 cm-2. IV. CONCLUSION The development of the surface channel flatband architecture has enabled the fabrication of well-behaved MOSFETs with mobilities of up to 4300 cm2/V·s which are sustained at high values up to channel carrier densities of 1x1013 cm-2; similar to the characteristics of buried channel devices. This behavior, in contrast to inversion channel devices, arises as a direct consequence of the carrier and vertical electric field distributions in the flatband architecture, and indicates the potential of this materials architecture solution for future low power, highly scaled n-channel CMOS. REFERENCES [1] International Technology Roadmap for Semiconductors, 2009. [Online]. Available: http://www.itrs.net/Links/2009ITRS/Home2009.htm [2] H. Wong, D. Frank and P. Solomon, “Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation.”, IEDM Tech. Dig., pp. 407-410, 1998. [3] D.-H. Kim and J. del Alamo, “30-nm InAs PHEMTs With fT = 644 GHz and fmax = 681 GHz.”, IEEE Electron Device Lett., vol. 31, no. 8 pp. 806 – 808, 2010. [4] M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, W. Rachmady, U. Shah, and Robert Chau, “Advanced high-κ gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications.”, IEDM Tech. Dig., pp. 319-322, 2009. [5] Y. Q. Wu, M. Xu, R.S. Wang, O. Koybasi and P. D. Ye, “High Performance Deep-Submicron Inversion-Mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/µm: New HBr pretreatment and channel engineering.”, IEDM Tech. Dig., pp. 323-326, 2009. [6] J. Huang, N. Goel, H. Zhao, C. Y. Kang, K.S. Min, G. Bersuker, S. Oktyabrsky, C.K. Gaspe, M.B. Santos, P. Majhi, P. D. Kirsch, H.-H. Tseng, J.C. Lee, and R. Jammy, “InGaAs MOSFET performance and reliability improvement by simultaneous reduction of oxide and interface charge in ALD (La)AlOx/ZrO2 gate stack.”, IEDM Tech. Dig., pp. 335-338, 2009. [7] D. Lin, N. Waldron, G. Brammertz, K. Martens, W.-E Wang, S. Sioncke, A. Delabie, H. Bender, T. Conard, W. H. Tseng, J. C. Lin, K. Temst, A, Vantomme, J. Mitard, M. Caymax, M. Meuris, M. Heyns, T. Hoffmann, “Exploring the ALD Al2O3/In0.53Ga0.47As and Al2O3/Ge Interface Properties: A Common Gate Stack Approach for Advanced III-V/Ge CMOS.” ECS Transactions, vol. 28, no. 5 pp. 173-183, 2010. [8] A. Ali, H. Madan, S. Koveshnikov and S. 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Advanced high-κ gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications.”,

Arsenic Decapping and Half-Cycle Reactions during Atomic Layer Deposition of

Atomically abrupt and unpinned Al2O3/In0.53Ga0.47As interfaces: Experiment and simulation.”,

Border Traps in Al2O3/In0.53Ga0.47As (100) Gate Stacks and Their Passivation by Hydrogen Anneals,”

Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation.”,

Enhancement-Mode GaAs MOSFETs with an In0.3Ga0.7As Channel, a Mobility of over 5000 cm 2/Vs and Transconductance of over 475 µS/µm”,

High Performance Deep-Submicron Inversion-Mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/µm: New HBr pretreatment and channel engineering.”,

High performance In0.7Ga0.3As metal-oxide-semiconductor transistors with mobility >4400 cm 2/Vs using InP barrier layer.”

InGaAs MOSFET performance and reliability improvement by simultaneous reduction of oxide and interface charge

Roadmap for Semiconductors,

Small-signal response of inversion layers in high-mobility In0.53Ga0.47As MOSFETs made with thin high-κ dielectrics.”

Electron mobility in surface- and buried- channel flatband In0.53Ga0.47As MOSFETs with ALD Al2O3 gate dielectric.

Enlighten: Publications

Steven J. Bentley

Martin Holland

Xu Li

Gary W. Paterson

Haiping Zhou

Olesya Ignatova

Douglas Macintyre

Stephen Thoms

Asen Asenov

Byungha Shin

Jaesoo Ahn

Paul C. McIntyre

Iain G. Thayne

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Electron Mobility in Surface- and Buried-Channel Flatband $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ MOSFETs With ALD  $\hbox{Al}_{2}\hbox{O}_{3}$ Gate Dielectric

http://eprints.gla.ac.uk/52717/1/ID52717.pdf

Electron mobility in surface- and buried- channel flatband In<sub>0.53</sub>Ga<sub>0.47</sub>As MOSFETs with ALD Al<sub>2</sub>O<sub>3</sub> gate dielectric.

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