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research
Effective Interconnect Networks Design in CMOS 45 nm Circuits to Joint Reductions of XT and Delay for Transmission of Very High Speed Signals
Authors
Sébastien De Rivaz
Denis Deschacht
+3 more
Alexis Farcy
Bernard Flechet
Thierry Lacrevaz
Publication date
16 December 2010
Publisher
HAL CCSD
Abstract
International audienceN/
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HAL Université de Savoie
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oai:HAL:lirmm-00546304v1
Last time updated on 09/11/2016
HAL Descartes
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oai:HAL:lirmm-00546304v1
Last time updated on 14/04/2021
Hal - Université Grenoble Alpes
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oai:HAL:lirmm-00546304v1
Last time updated on 11/11/2016