The electronics for the electromagnetic and hadronic calorimeters of LHCb is under design. The 32 channel-9U front-end board offers the complete front-end and readout electronics for every channel including original shaping, 12bit-40MHz ADC, digital filtering and latency for level 0 and level 1 triggers. The clipped PM input signal is integrated during 25ns, but also delayed then subtracted to itself 25ns later which allows performant pile up independence. This board also includes the first processing levels of the L0 calorimeter trigger. A 16 channel-6U prototype board has been designed and used at CERN in test beam in 1999

Beigbeder-Beau, C

Bernier, R E

Breton, D

Cacéres, T

Callot, O

Cros, P

Delcourt, B

Hrisoho, A T

Jean-Marie, B

Lefrançois, J

Tocut, V

Truong, K D

Videau, I

CERN Document Server

The Front-End Electronics for LHCb calorimetersC.Beigbeder, R.Bernier, D.Breton, T.Cacéres,P.Cros, A. Hrisoho, V. Tocut, K. TruongLaboratoire de l’Accélérateur LinéaireBP 34 – 91898 Orsay Cedex - France1. ABSTRACTThe electronics for the electromagnetic and hadroniccalorimeters of LHCb is under design. The 32 channelfront-end board offers the complete front-end and readoutelectronics for every channel including original shaping,12bit-40MHz ADC, digital filtering and latency for level0 and level 1 triggers. The clipped PM input signal isintegrated within 25ns, but also delayed then subtracted toitself 25ns later what allows performant pile upindependence. This board also includes the firstprocessing levels of the L0 calorimeter trigger.A 16 channel prototype board has been designedand used at CERN in test beam last summer.2. INTRODUCTIONThe electromagnetic and hadronic calorimeterscurrently designed for LHCb are lead-scintillatorsandwiches employing the “Shashlick” technology. Theoutput of the plastic fibers is equipped with phototubes.The readout system will have to deal with 6000 channelsfor the Ecal and 1500 for the Hcal.3. REQUIREMENTSThe main requirement for LHCb electronics is thepile-up rejection. Indeed the residue of a previous signalon the current sample has to be less than 1% after 25ns.This implies to work both on the PM signal and on theshaping. Shaped data has to be sampled at 40MHz on 12bits then to undergo pedestal subtraction for rejecting LFnoise and to be transcoded within LUTs into energy over8 bits for trigger data and 12 bits for readout data. Thelatter has to be buffered during the L0 latency, to bederandomized and then rebuffered for the level 1 latency.After the level 1 trigger, an extended zero suppression hasto be performed before sending the formatted event to theDAQ.There are also trigger elements sitting in the front-end crate. The first stages concern the seek for localmaxima inside groups of 512 channels, with a validationby the Preshower and Pad Chamber data.4. FRONT-END OVERVIEWFig 1 describes the Front-End crate and its maininterconnections. The PM side elements are connected tothe Front-End board through 10 meters of coaxial cables.There are 16 FEBs in the crate, each receiving 32 signals.The output of these boards are connected to the custombackplane, sending signals using LVDS levels to theEvent Filter. This board is in charge of performing theadvanced zero suppression and the event formatting afterlevel 1. Data is then sent to the DAQ through opticallinks. The Crate Controller is in charge of driving theserial link which is used for loading the hardware and ofdistributing the TTC signals. At last, the TriggerValidation Board receives the local maxima coming outfrom the FEB, then validates it with the Pad Chamber andPreshower information and finally searches for  theresidual maxima over the two half crates. The resultingwords are sent to the Trigger Main Selection cratethrough optical links.Fig 1 : overview of the Front-End Crate5. THE FRONT-END BOARDFig 2 shows the block diagram of the 32 channelFront-End board. This is a 9U board using VMEmechanics but deserting the VME bus. This one will bereplaced by a serial bus which has still to be defined.Let’s follow the main data path inside the board. Itstarts with the four 8-channel coaxial input connectors.Then signals goes into the PM and cable compensationbefore entering the analog chip. After a 12bit ADCconversion, data undergoes a pedestal subtraction with thesmallest of the two previous samples. This subtraction isintended to reduce the high bandwidth noise of theintegrator, and the two samples are used not to degradethe pile-up rejection. Then data is converted into energywithin two LUTs, one for the trigger which outputs 8 bitwords, the other for the readout data which outputs 12 bitwords in a pseudo floating format. The latter data is thensent to the L0 latency pipeline, L0 derandomizer and L1latency buffer. After L1 trigger, it is sent across thebackplane using LVDS levels towards the EventFormatter.At the right top of the board, trigger data is firstadded in squares of 4 cells while preserving the originalgranularity, then filtered looking for the local maximumon the board. The latter is sent with its address (total of 13bits) using LVDS levels towards the Trigger ValidationBoard.Fig 2 : block diagram of the Front-End boardBeside those data paths, some utility functions havebeen implemented. One can adjust the sampling time ofevery ADC on the board thanks to programmable delaychips with a precision of 1 ns. A functionnal analogcalibration has also been implemented to allow checkingof the complete readout chain. This has already beenuseful during the test beam operations.6. THE FRONT-END ELEMENTSThe purpose of those elements is to shape the PMpulses in less than 25ns to avoid electronics pile-up. Thespecifications on both extremities are the following :• At the input : the PM maximum current is 20mAover 25 ohms.• At the output : the ADC input dynamic range is 1Vunder 250 ohms.• The residue after 25 ns has to be smaller than 1%.• The sampling area should cover +- 3ns with a 1%precision.• The RMS noise has to be < 1 ADC count (250uV).• The deterioration of the statistic fluctuation due tothe apparatus has to stay under a factor 2.To fulfil the above requirements, two problems willhave to be solved. The first one concerns the PM signal.If one looks at Fig 3, the PM output current has a fast risetime but a slow decay that goes over at least the twoconsecutive samples at 40 MHz. It thus needs to be pulledto zero after 10ns to ensure the zero pile-up requirement.The remaining area is on the order of 60% of the originalone.Fig 3 : PM output pulseTo realize this cut on the signal, the clipping circuiton the left of Fig 4 will be used. It consists in a short 1meter cable located at the output of the PM base. Itderivates the signal towards a variable network which willsend back a inverted part of the signal. As both the sourceand reflected signals are negative exponentials, theirsuperposition leads to zero. The demonstration is givenon the top plot of Fig 5.Fig 4 : Front-End ElectronicsNow that the input signal has been shaped, we haveto measure the energy deposited in the calorimeter. Thecorresponding information is the area of the PM signal.The best way to measure it without deteriorating toomuch the statistic fluctuation is to integrate this signal in acapacitor (Cf). The induced difficulty becomes to emptythis capacitor. Two ways are possible :• Use a switch mounted in parallel but this systeminduces a dead time when the capacitor is beingemptied, what implies the use of two integrators inparallel and a multiplexor.• Subtract in a linear way the signal to itself thanks to aspecific configuration.The latter is the chosen solution. The configurationappears in the middle of Fig 4. The input signal of theanalog chip is derivated, delayed by 25ns, then subtractedto itself thanks to the differential buffer. The latter hasalso in charge the division of the input current to adapt itto the small value of Cf which ensures a fast rise time tothe integrator.Fig 5 : simulated input and output pulses of theintegratorBetween the buffer and the integrator, there is anexternal AC coupling that allows to separate the DClevels. The small value of Cf allows to load it fast and tooffer a nice plateau at the top of the signal (see bottomplot of Fig 5).Fig 6 : schematics of the analog chip.Fig 6 shows the schematics of the analog chip. The2K resistor at the output of the buffer is used for replacinga 1mA current source that would produce an offsetcurrent and more noise with the same power supplies thanthe resistor. Obviously, the buffer has a current output asthe input impedance of the integrator is small (200 ohms)compared to the 2K of the resistor.The integrator schematics is based on a cascodeamplifier. Its open loop gain is high (60dB), it’s fast asthere is no Miller effect on the input PMOS, and itproduces very low noise. On the other hand, there is aneed for an emitter follower at the output not to degradethe gain by the charge impedance. In our case, as thecharge is only 350 ohms, another follower has beenmounted on the board using discrete elements. The decaytime of the integrator is linked to the 2K resistor whatleads to a value of 6us.Fig 7 : layout of the analog chipFig 7 shows the layout of the current version of theanalog chip. Up to now, three versions have beensubmitted in only 6 months. This is due to the pression ofthe test beam of last summer. The main difficulty thatappeared was a resistor in the gate access to the inputPMOS of the integrator. This was due to a bad polysilicondesign and introduced noise and instability in the chipresponse. This problem was fixed and the chips receivedtwo days before the test beam were fully operationnal.When mounted on test bench at LAL, the chip offered theresults shown in Fig 8.Fig 8 : real signals on test benchOn this plot, the input pulse derives from a generatorand is clipped as the real PM signal. The output signalshows a nice flat top in concordance with the simulations.The global preliminary results from this test bench aregiven in Fig 9.Fig 9 : first results from the test benchThese results show a good adequation betweensimulation and real circuit, except for the gm of the inputtransistor. This is due to simulation models and alsoexplains the mismatches in the rise time and the inputimpedance of the integrator.7. THE PROTOTYPE FRONT-END BOARDThe prototype FEB shown on Fig 10 is a 16 channelboard which has been designed targeting the test beam oflast summer. It comprises the same readout chainexcepting the L1 buffer. Moreover, some extrafunctionnalities as the spying of the raw data at the outputof the ADCs have been implemented. This allows tocrosscheck offline the subtracted data with their source.Fig  10 : prototype of the Front-End boardAnother interesting purpose of this board is theconfiguration state machine implemented in the VMEinterface Altera. It allows to configure all the otherFPGAs on the board in an interactive way, permitting todebug the board easily (even far from home through ftp)and also to modify the functionnality of the FPGAs fortest purposes.Fig 11 : top layer of the prototype FEBFig 11 offers a picture of the board. On the left side,one can see the 2 x 8 channel input connectors, followedby the PM and cable compensation networks and thedelay lines. The four 4 channel analog chips are followedby half the ADCs and the LUTs. All the big FPGAs(10K50 and 6K16) are on the other side of the board,together with the other half of the ADCs.8. THE TEST BEAM ENVIRONMENTThis board was installed on test beam in the setupshown in Fig 12.Fig 12 : test beam setup at CERNOne can remark here that two VME master crates canbe connected to the remote electronics. This is intendedfor debugging and monitoring purposes. Indeed, whenelectronics is installed at CERN for test beam, local DAQstill needs to be debugged. The MacIntosh interactive testsoftware, which also provides data acquisition, and thepossibilities of live insertion of the SPAC bus thus allowto start the debugging phase of the hardware whilepermitting crosscheck of the readout data with the oneread by the standard DAQ. This is then a very efficientway of setting up the system in a very short time.9. TEST BEAM RESULTSThe first measurements made on test beam wererelated to the signal coming from the PMs. It is plotted ontop of Fig 13.Fig 13 : real signals on test beamOne can remark that the width of the signal is muchlarger than on test bench. This was due to some problemswith the quality of the fiber inside the Shashlick and ofthe microcoaxial cable. Nevertheless, the shape at theoutput of the integrator (bottom plot) looks quite goodwith a large top where sampling can be clean.The following step was to compare the new 40MHzelectronics with the “old” LeCroy one. Data was thustaken on the same channel through the two differentpaths. The comparison is plotted on Fig 14.Fig 14 : new electronics vs LeCroy ADCsThe straight line proved the good level offunctionnality of the new electronics and data was thentaken with the latter.Fig 15 presents the results of an ECal run. 6 samplesare plotted successively. The signal is centered on thesample 5 (third one). On the sample 3, one can observethe noise distribution. This corresponds to a RMS of 2.5ADCC. The sample 4 shows that the signal is wider thanon the Fig 13 as there is already some data 25ns beforethe peak. This was due to some problems with the PMused at this occasion.Fig 15 :  6 samples from an Ecal runOn the samples 6 and 7 appears the result from thesubtraction of the smallest of the two previous samples.On sample 8, we’re back to the baseline.10. NEXT STEPS OF THE DEVELOPMENTThe previous measurements made on test beam provethe consistency of the electronics which has beendesigned. We are currently concentrating on the variousnoise sources to reduce the total noise on the board under1.5 ADCC.The next steps of the developments for thiselectronics are the following :• Concerning the Front_end Board : A new version of the analog chip including asecond emitter follower by early 2000 Implementation of the trigger part of the board Study of the L1 buffering hardware Extension to a 9U/32 channel board• Study of the fast backplane using LVDS signals• Study of the Event Filter (which provides advancedzero suppression and event formatting)• Study of the Crate Controller (which includes serialaccess bus and TTC)• Study of the Trigger Validation Board (whichprepares the candidates for the L0 trigger MainSelection Crate)11. REFERENCESFor completing the information given in this paper,one could have a fruitful look to the following notes : J.Christiansen, “Requirements to the L0 front-endelectronics”, LHCb technical note, July 30th 1999 C.Beigbeder et al., “A Joint Proposal for the Level 0Calorimetric Triggers”, LHCb 99-017, June 7th 1999 D.Breton et al., “SPAC : Serial Protocol for the AtlasCalorimeter “, www.lal.in2p3.fr/technique/se/spac

The front end electronics for LHCb calorimeters

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