We present the status of our investigations on the LISA Phasemeter. The new prototype is based on a custom-designed breadboard with four high-speed ADC and two DAC channels, extended readout capabilities and a large FPGA (field programmable gate array). The required main functionalities and performance of the prototype have been demonstrated in laboratory conditions. © 2009 IOP Publishing Ltd

Bykov, Iouri

Danzmann, Karsten

Delgado, Juan Jose Esteban

Heinzel, Gerhard

Marín, Antonio Francisco Garcia

Journal of Physics : Conference Series

We present the status of our investigations on the LISA Phasemeter. The new prototype is based on a custom-designed breadboard with four high-speed ADC and two DAC channels, extended readout capabilities and a large FPGA (field programmable gate array). The required main functionalities and performance of the prototype have been demonstrated in laboratory conditions

Bykov, I.

Esteban Delgado, J.

Marin, A.

Heinzel, G.

Danzmann, K.

MPG.PuRe

LISA phasemeter development: AdvancedprototypingIouri Bykov, Juan Jose´ Esteban Delgado, Antonio Francisco Garc´ıaMar´ın, Gerhard Heinzel, Karsten DanzmannInstitute for Gravitational Physics of the Leibniz University Hannoverand Max Planck Institute for Gravitational Physics (Albert Einstein Institute), GermanyE-mail: Iouri.bykov@aei.mpg.deAbstract.We present the status of our investigations on the LISA Phasemeter. The new prototypeis based on a custom-designed breadboard with four high-speed ADC and two DAC channels,extended readout capabilities and a large FPGA (field programmable gate array). The requiredmain functionalities and performance of the prototype have been demonstrated in laboratoryconditions.1. IntroductionThe main task to be implemented by the LISA Phase Measurement System (PMS) is the phasereadout of the beat note coming from the photo-detectors on the optical benches. The requiredphase sensitivity is 2pi × 10−6 rad/√Hz on the frequency range from 0.1mHz to 100mHz. Thiscorresponds to the detection of pathlength variations between the free floating test masses inthe picometer range, required for the observation of gravitational waves. These accuracy inthe phase measurements must be ensured over a frequency range of the heterodyne signal be-tween 2 and 20MHz. Apart from this, the PMS must be able to isolate and extract the phasefrom the various beat notes contained in the incoming photodiode signal. The most suitablephasemeter architecture, which can provide the required accuracy, is based on a so-called digitalphase-locked loop (DPLL) [1, 2]. Once the phase readout has been performed, the back-endprocessing of the PMS must implement a high bandwidth laser phase-locking control system, aswell as inter-spacecraft laser ranging, data communication and clock synchronization [4].To achieve these goals, a new custom-designed prototype board has been recentlymanufactured taking as an starting point the experience from previous prototypes [3]. It consistsof a multi-channel PMS with high-speed digital processing capabilities, high bandwidth analoginput/output interfaces and full signal visibility.2. Implementation of the digital phase-locked loopFigure 1 shows a single channel of the developed phasemeter architecture. To avoid aliasing,the incoming signal is processed with an integrated analog LC-filter. After filtering, the signalis digitized in a low-noise analog-to-digital converter (ADC) at 50MHz sampling rate and fedinto the FPGA. Here, the phase detection begins with the multiplication of the incoming beat7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/012017c© 2009 IOP Publishing Ltd 1note with a sine signal generated by a numerically controlled oscillator (NCO), consisting of alookup sine table (LUT), phase accumulator (PA) and a phase increment register (PIR). Theresult of the multiplication, after a low-pass filter (LPF), is proportional to the phase differencebetween the input signal and the NCO. Therefore, this result can be used as error signal in acontrol loop to adjust the phase of the NCO to the incoming beat note. This is done with aproportional-integral controller (PIC) that transforms the phase error in a feedback signal forthe PIR.Figure 1. Block diagram of the phasemeter core design.The primary results of the PMS are the values of the PIR and the PA registers, withcorrespond to frequency and phase of the input signal, respectively. Additionally, the filteredoutput signals of the I-LUT and Q-LUT branches can be used for phase measurement corrections.The downsampled data can be readout into a floating-point computing system (e.g. PC) throughan integrated enhanced parallel port (EPP). It is also possible to employ a high-speed digitalinput/output board (DIOB) with direct memory access feature to test internal intermediateresults of the PMS, thus providing extended opportunities for investigation of the system andefficient debugging.3. Phase measurement techniqueFigure 2 illustrates the detailed phase reconstruction of the DPLL algorithm presented previouslyin Section 2. The binary value stored in the phase accumulator (PA), consists of a fixed-pointpart A and fractional part B with a bit depth N. After multiplication by 2pi and proper scaling,its results is the current phase value of the input signal in radians:ϕ = 2Api +B2N. (1)7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/0120172Figure 2. Phase reconstruction using phase accumulator.4. Hardware DescriptionFigure 3 shows one of the prototypes of the design presented here that has been recently manu-factured. This design implements four channels in one board and provides enhanced processingcapabilities. For this purpose, ACTEL FPGAs are the most suitable choice due to their flexi-bility on design and space-flight compatibility. Our board supports up to 3Million system gateswith 147 high-performance inputs/outputs (I/Os). The software is designed in a very high speedintegrated circuit hardware description languages (VHDL).The digitization of the input beat note signals in the frequency range 2-20MHz is performedby four A/D-converters (AD9446-100). The current prototype works with an unique internalquartz clock set at 50MHz, but it is also possible to set an arbitrary clock by mean of anexternal port. Two D/A converters (AD9744) in combination with output filters are intendedto be used for laser frequency stabilization purposes. The characteristics of the DAC enablealso two important features for LISA: first, the control of different analog actuators in the LISAsetup and second, the implementation of a laser-modulation unit with the use of an electro-opticmodulator (EOM). This way, the breadboard can be used in a modulator/demodulator schemeto perform laser ranging [4]. Additionally, the four input channel can measure individually thephase of each quadrant of the photodiodes and deliver alignment signals for orientation control.Figure 3. 4-channel prototype of LISA Phasemeter with extended signal processing and readoutopportunities. EPP with output rate up to 1MB/s. Digital input/output (DIO) with maximal rate of2GB/s.7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/01201735. Experimental resultsIn contrast to analog-based PMS implementations, a digital development makes it possible toupdate the firmware and eliminate the temperature drift. However, the digitization process suf-fers from quantization noise and subsequently the errors in the measurement need to be takeninto consideration. In this section we present preliminary results in the assessment of the influ-ence of these noise sources in our design.Figure 4 presents the results of the first experiment, where the input signal was generatedby an additional NCO implemented in the same FPGA as the PMS. The aim of the experimentwas to verify the functionality and noise performance of the DPLL. The measurement shows aflat noise floor over the whole frequency range down to 1mHz, limited only by the quantificationnoise of the ADC and the finite resolution inside the FPGA. The spikes at high frequencies arecurrently a subject of investigations, most probably being caused by suboptimal performance ofthe anti-aliasing filter applied to the output data before decimation.10-810-710-610-510-410-310-210-110-4 10-3 10-2 10-1 100 101Phase noise [rad/√Hz]frequency [Hz]Phase noise 5 MHz carrierFigure 4. Noise performance of the phasemeter with 5MHz input signal, generated by an additionalNCO implemented in FPGA.The next experiment was made in more realistic conditions: an external function generator,locked to the clock generator of the phasemeter, was used as input signal. In such conditions allthe hardware was tested, including analog frontend and ADCs. The results of the experimentare shown in Figure 5. The noise behavior measured in this configuration is clearly limited bythe performance of the external lock used by the PLL of the generator.Another area of research concerns the back-end processing of the measured phase to performranging between the spacecraft: using the current breadboard, a delay-locked loop (DLL) systemhas been implemented. This system will enable to measure the light propagation time delay. Forthis purpose, the phase of laser carrier is modulated and a pseudo-random-noise codes (PRN)7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/012017410-810-710-610-510-410-310-210-110-4 10-3 10-2 10-1 100 101Phase noise [rad/√Hz]frequency [Hz]Phase noise 5 MHz carrierFigure 5. Noise performance of the phasemeter with 5MHz input signal, generated by an externalfunction generator.are transmitted to the remote satellites. The correlation properties of the PRN enable datacommunication and synchronization between different spacecraft[4].6. ConclusionsA custom phasemeter prototype has been developed and its functionality demonstrated withelectrical signals. The design aims to implement in a single platform the interferometric phasereadout as core processing and a phase-locking control system, optical ranging, data transferand clock synchronization as back end processing. The experimental results show that the newversion of the phasemeter meets the requirement of 2pi × 10−6 rad/√Hz for the phase readoutin the case of internally simulated input signals. We thus conclude that the current prototypecan be expected to be a key component for the LISA interferometry test bench.7. References[1] Shaddock D, Ware B, Halverson P, Spero R, Klipstein B 2006 Overview of the LISA Phasemeter AIP ConfProc. 873 654-60[2] Wand V, Guzman F, Heinzel G, Danzmann K 2006 LISA Phasemeter Development AIP Conf Proc. 873689-96[3] Wand V 2007 Interferometry at low frequencies: Optical phase measurement for LISA and LISA Pathfinder.Ph.D Thesis, University Hannover[4] Esteban J.J, Bykov I, Garc´ıa Mar´ın A.F, Heinzel G, Danzmann K 2008 Optical ranging and data transferdevelopment for LISA J. Phys.: Conf. Series. this issue7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/0120175

English

LISA phasemeter development: advanced prototyping

Institutional Repository of Leibniz Universität Hannover

This content has been downloaded from IOPscience. Please scroll down to see the full text.Download details:IP Address: 194.95.157.184This content was downloaded on 05/05/2017 at 08:32Please note that terms and conditions apply.LISA phasemeter development: Advanced prototypingView the table of contents for this issue, or go to the journal homepage for more2009 J. Phys.: Conf. Ser. 154 012017(http://iopscience.iop.org/1742-6596/154/1/012017)Home Search Collections Journals About Contact us My IOPscienceYou may also be interested in:Optical testbed for the LISA phasemeterT S Schwarze, G Fernández Barranco, D Penkert et al.Phasemeter core for intersatellite laser heterodyne interferometry: modelling, simulations andexperimentsOliver Gerberding, Benjamin Sheard, Iouri Bykov et al.The design and construction of a prototype lateral-transfer retro-reflector for inter-satellitelaser rangingR L Ward, R Fleddermann, S Francis et al.Optical ranging and data transfer development for LISAJuan José Esteban, Iouri Bykov, Antonio Francisco García Marín et al.Implementation of the phasemeter for LISA LTPA M Cruise, D Hoyland and S M AstonDesign of a ``Digital Atlas Vme Electronics'' (DAVE) moduleM Goodrick, D Robinson, R Shaw et al.Remote access to Xilinx programmable devices in the CSC endcap muon electronic system at CMSJ Liu, M Matveev and P PadleyInterferometry development for LISA and SMART-2O Jennrich, P McNamara, D Robertson et al.A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-m CMOSLin Li, Ren Junyan and Ye FanLISA phasemeter development: AdvancedprototypingIouri Bykov, Juan José Esteban Delgado, Antonio Francisco GarćıaMaŕın, Gerhard Heinzel, Karsten DanzmannInstitute for Gravitational Physics of the Leibniz University Hannoverand Max Planck Institute for Gravitational Physics (Albert Einstein Institute), GermanyE-mail: Iouri.bykov@aei.mpg.deAbstract.We present the status of our investigations on the LISA Phasemeter. The new prototypeis based on a custom-designed breadboard with four high-speed ADC and two DAC channels,extended readout capabilities and a large FPGA (field programmable gate array). The requiredmain functionalities and performance of the prototype have been demonstrated in laboratoryconditions.1. IntroductionThe main task to be implemented by the LISA Phase Measurement System (PMS) is the phasereadout of the beat note coming from the photo-detectors on the optical benches. The requiredphase sensitivity is 2π × 10−6 rad/√Hz on the frequency range from 0.1mHz to 100mHz. Thiscorresponds to the detection of pathlength variations between the free floating test masses inthe picometer range, required for the observation of gravitational waves. These accuracy inthe phase measurements must be ensured over a frequency range of the heterodyne signal be-tween 2 and 20 MHz. Apart from this, the PMS must be able to isolate and extract the phasefrom the various beat notes contained in the incoming photodiode signal. The most suitablephasemeter architecture, which can provide the required accuracy, is based on a so-called digitalphase-locked loop (DPLL) [1, 2]. Once the phase readout has been performed, the back-endprocessing of the PMS must implement a high bandwidth laser phase-locking control system, aswell as inter-spacecraft laser ranging, data communication and clock synchronization [4].To achieve these goals, a new custom-designed prototype board has been recentlymanufactured taking as an starting point the experience from previous prototypes [3]. It consistsof a multi-channel PMS with high-speed digital processing capabilities, high bandwidth analoginput/output interfaces and full signal visibility.2. Implementation of the digital phase-locked loopFigure 1 shows a single channel of the developed phasemeter architecture. To avoid aliasing,the incoming signal is processed with an integrated analog LC-filter. After filtering, the signalis digitized in a low-noise analog-to-digital converter (ADC) at 50 MHz sampling rate and fedinto the FPGA. Here, the phase detection begins with the multiplication of the incoming beat7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/012017c© 2009 IOP Publishing Ltd 1note with a sine signal generated by a numerically controlled oscillator (NCO), consisting of alookup sine table (LUT), phase accumulator (PA) and a phase increment register (PIR). Theresult of the multiplication, after a low-pass filter (LPF), is proportional to the phase differencebetween the input signal and the NCO. Therefore, this result can be used as error signal in acontrol loop to adjust the phase of the NCO to the incoming beat note. This is done with aproportional-integral controller (PIC) that transforms the phase error in a feedback signal forthe PIR.Figure 1. Block diagram of the phasemeter core design.The primary results of the PMS are the values of the PIR and the PA registers, withcorrespond to frequency and phase of the input signal, respectively. Additionally, the filteredoutput signals of the I-LUT and Q-LUT branches can be used for phase measurement corrections.The downsampled data can be readout into a floating-point computing system (e.g. PC) throughan integrated enhanced parallel port (EPP). It is also possible to employ a high-speed digitalinput/output board (DIOB) with direct memory access feature to test internal intermediateresults of the PMS, thus providing extended opportunities for investigation of the system andefficient debugging.3. Phase measurement techniqueFigure 2 illustrates the detailed phase reconstruction of the DPLL algorithm presented previouslyin Section 2. The binary value stored in the phase accumulator (PA), consists of a fixed-pointpart A and fractional part B with a bit depth N. After multiplication by 2π and proper scaling,its results is the current phase value of the input signal in radians:ϕ = 2Aπ +B2N. (1)7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/0120172Figure 2. Phase reconstruction using phase accumulator.4. Hardware DescriptionFigure 3 shows one of the prototypes of the design presented here that has been recently manu-factured. This design implements four channels in one board and provides enhanced processingcapabilities. For this purpose, ACTEL FPGAs are the most suitable choice due to their flexi-bility on design and space-flight compatibility. Our board supports up to 3 Million system gateswith 147 high-performance inputs/outputs (I/Os). The software is designed in a very high speedintegrated circuit hardware description languages (VHDL).The digitization of the input beat note signals in the frequency range 2-20 MHz is performedby four A/D-converters (AD9446-100). The current prototype works with an unique internalquartz clock set at 50 MHz, but it is also possible to set an arbitrary clock by mean of anexternal port. Two D/A converters (AD9744) in combination with output filters are intendedto be used for laser frequency stabilization purposes. The characteristics of the DAC enablealso two important features for LISA: first, the control of different analog actuators in the LISAsetup and second, the implementation of a laser-modulation unit with the use of an electro-opticmodulator (EOM). This way, the breadboard can be used in a modulator/demodulator schemeto perform laser ranging [4]. Additionally, the four input channel can measure individually thephase of each quadrant of the photodiodes and deliver alignment signals for orientation control.Figure 3. 4-channel prototype of LISA Phasemeter with extended signal processing and readoutopportunities. EPP with output rate up to 1 MB/s. Digital input/output (DIO) with maximal rate of2GB/s.7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/01201735. Experimental resultsIn contrast to analog-based PMS implementations, a digital development makes it possible toupdate the firmware and eliminate the temperature drift. However, the digitization process suf-fers from quantization noise and subsequently the errors in the measurement need to be takeninto consideration. In this section we present preliminary results in the assessment of the influ-ence of these noise sources in our design.Figure 4 presents the results of the first experiment, where the input signal was generatedby an additional NCO implemented in the same FPGA as the PMS. The aim of the experimentwas to verify the functionality and noise performance of the DPLL. The measurement shows aflat noise floor over the whole frequency range down to 1 mHz, limited only by the quantificationnoise of the ADC and the finite resolution inside the FPGA. The spikes at high frequencies arecurrently a subject of investigations, most probably being caused by suboptimal performance ofthe anti-aliasing filter applied to the output data before decimation.10-810-710-610-510-410-310-210-110-4 10-3 10-2 10-1 100 101Phase noise [rad/√Hz]frequency [Hz]Phase noise 5 MHz carrierFigure 4. Noise performance of the phasemeter with 5MHz input signal, generated by an additionalNCO implemented in FPGA.The next experiment was made in more realistic conditions: an external function generator,locked to the clock generator of the phasemeter, was used as input signal. In such conditions allthe hardware was tested, including analog frontend and ADCs. The results of the experimentare shown in Figure 5. The noise behavior measured in this configuration is clearly limited bythe performance of the external lock used by the PLL of the generator.Another area of research concerns the back-end processing of the measured phase to performranging between the spacecraft: using the current breadboard, a delay-locked loop (DLL) systemhas been implemented. This system will enable to measure the light propagation time delay. Forthis purpose, the phase of laser carrier is modulated and a pseudo-random-noise codes (PRN)7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/012017410-810-710-610-510-410-310-210-110-4 10-3 10-2 10-1 100 101Phase noise [rad/√Hz]frequency [Hz]Phase noise 5 MHz carrierFigure 5. Noise performance of the phasemeter with 5MHz input signal, generated by an externalfunction generator.are transmitted to the remote satellites. The correlation properties of the PRN enable datacommunication and synchronization between different spacecraft[4].6. ConclusionsA custom phasemeter prototype has been developed and its functionality demonstrated withelectrical signals. The design aims to implement in a single platform the interferometric phasereadout as core processing and a phase-locking control system, optical ranging, data transferand clock synchronization as back end processing. The experimental results show that the newversion of the phasemeter meets the requirement of 2π × 10−6 rad/√Hz for the phase readoutin the case of internally simulated input signals. We thus conclude that the current prototypecan be expected to be a key component for the LISA interferometry test bench.7. References[1] Shaddock D, Ware B, Halverson P, Spero R, Klipstein B 2006 Overview of the LISA Phasemeter AIP ConfProc. 873 654-60[2] Wand V, Guzman F, Heinzel G, Danzmann K 2006 LISA Phasemeter Development AIP Conf Proc. 873689-96[3] Wand V 2007 Interferometry at low frequencies: Optical phase measurement for LISA and LISA Pathfinder.Ph.D Thesis, University Hannover[4] Esteban J.J, Bykov I, Garćıa Maŕın A.F, Heinzel G, Danzmann K 2008 Optical ranging and data transferdevelopment for LISA J. Phys.: Conf. Series. this issue7th International LISA Symposium IOP PublishingJournal of Physics: Conference Series 154 (2009) 012017 doi:10.1088/1742-6596/154/1/0120175

LISA phasemeter development: Advanced prototyping

Marin, Antonio Francisco Garcia

Max Planck Society eDoc Server

Iouri Bykov

Juan José Esteban Delgado

Antonio Francisco García Marín

Gerhard Heinzel

Karsten Danzmann

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LISA phasemeter development: Advanced prototyping

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