Instruction level multithreading is a technique for tolerating long–
latency operations (e.g., cache misses) by switching the processor to another
thread instead of waiting for the completion of a lengthy operation. In block mul-
tithreading, context switching occurs for each initiated long–latency operation.
However, processor cycles during pipeline stalls as well as during context switch-
ing are not used in typical block multithreading, reducing the performance of
a processor. Dual block multithreading introduces a second active thread which
is used for instruction issuing whenever the original (main) thread becomes in-
active. Dual block multithreading can be regarded as a simple and specialized
case of simultaneous multithreading when two (simultaneous) threads are used
to issue instructions for a single pipeline. The paper develops a simple timed
Petri net model of a dual block multithreading and uses this model to estimate
the performance improvements of the proposed dual block multithreading
