Development of High-Speed, Low-fixed Latency Serial Links for the Router of ATLAS NSW sTGC Detector

Abstract

The ATLAS experiment at the Large Hadron Collider (LHC) needs to be upgraded in order to cope with the increased luminosity and particle rates expected for the High Luminosity LHC (HL­LHC) running. Part of the phase­1 upgrade, to be done in the 2018/19 shutdown, is the replacement of the present muon forward detector (wheel) by a new detector, the so called New Small Wheel (NSW). The NSW detector consists of two detector technologies and the work here is on the small­strip Thin­Gap Chambers (sTGC). For sTGC, it requires very high­speed electronic triggering of signal events. The data must be quickly digitized, serialized, and transmitted off­detector for computer processing. The serialized data is sent to the trigger processor through a routing system that serves as a switchyard for all active signals. Design requirements on the router are low latency and stable/predictable data transfer timing with high­speed serial links (4.8 Gbps). We describe a 4.8 Gbps (maximum 6.6 Gbps) serial link structure based on GTP transceivers embedded in Xilinx Artix­7 FPGA that uses an adapted cut­through switching method in the FPGA fabric logic to deal with the latency issue. A flexible routing algorithm developed to minimize signal loss will be discussed. The implementation of the whole process firmware and the latency test results achieved with this serial link system are presented and discussed