This note describes the VELO high voltage control software. The implementation of its structure as a PVSS Finite State Machine is emphasized. The main error conditions that may occur during operation is also discussed. The VELO HV software conforms to the specification of the VELO

De Capua, S

Eklund, L

Parkes, C

Rakotomiaramanana, B

CERN Document Server

LHCb-PUB-2009-02618/03/2010The VELO High Voltage SystemControl SoftwarePublic NoteReference: LHCb-PUB-2009-026Created on: December 1, 2009Prepared by: Barinjaka Rakotomiaramanana∗a,Chris Parkesa,Lars Eklunda,Stefano De Capua∗b*Corresponding authorsaUniversity of Glasgow,Department of Physics and AstronomybCERNThe VELO High Voltage System Control Software Ref: LHCb-PUB-2009-026Date: December 1, 2009Contents1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Overview of the High Voltage Control System . . . . . . . . . . . . . 23 PVSS Architecture . . . . . . . . . . . . . . . . . . . . . . . . 34 Structure of the High Voltage Control Software . . . . . . . . . . . . 35 The VELO High Voltage Finite State Machine . . . . . . . . . . . . . 46 Alarm and Error Conditions . . . . . . . . . . . . . . . . . . . . . 57 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8List of Figures1 Overview of the high voltage system control . . . . . . . . . . . . . . 32 Representation of the architecture of PVSS . . . . . . . . . . . . . . 43 Overview of the high voltage control software structure . . . . . . . . . 54 Layout of the VELOA HV panel . . . . . . . . . . . . . . . . . . . 65 Layout of the VELOA HVBOARD01 panel . . . . . . . . . . . . . . . 66 Layout of the VELOA HV BOARD00 CH00 panel . . . . . . . . . . . . 77 Organigram showing the main VELO HV Finite State Machine structure . . 7page 1The VELO High Voltage System Control Software Ref: LHCb-PUB-2009-0262 Overview of the High Voltage Control System Date: December 1, 20091 IntroductionThe Vertex Locator (VELO) [1] high voltage system requires powerful, flexible and reliablesoftware that is easy to maintain. Moreover, LHCb uses a distributed control system whichallows inter-process communication between processes running on several different PCs.The software that was chosen for LHCb, hence the VELO high voltage system, is PVSS [2].An overview of the HV control system is given in section 2. The PVSS architecture for theHV system is presented in section 3. Section 4 provides a description of the structure of theHV control software. PVSS has the following advantages:• Powerful commercial product which supports distributed systems and includes toolsfor object-like device description, archiving, alarms, user-created panels and scripts.• It is a Supervisory Control and Data Acquisition [3] (SCADA) framework and is usedto connect to hardware (or software) devices, acquire the data they produce and use itfor their supervision, i.e. to monitor their behaviour and to initialize, configure and op-erate them. Data structures have very flexible formats that can be exchanged betweenservers and clients; data can be sent on request or by subscription.• Provides an object-like data structure called ‘data points’ created to model the com-plexity of devices and data structures in the experiments. Data points are instances ofthese objects and can easily be created in large numbers as needed by the application.One can create an object of data points type that can be instantiated for each hardwareitem (an example is an actual online value of the voltage in one channel).• A PVSS ‘manager’ is available which permits exchange of data by a very simple mech-anism between data points in PVSS and other processes running on different PCs.• PVSS is the control system chosen for the LHC experiments. The Joint Controls Project[4] (JCOP) is part of the CERN IT/CO group and is a collaboration between the experi-ments and CERN support groups. JCOP has developed many commonly needed tools:a framework, interfaces to hardware devices, configuration tools, etc. PVSS 3.8 is usedwith the JCOP framework to control the ISEGa high voltage power supply modules andcrate. An ISEG Object linking and embedding Process Control (OPC) server providesinterface between the high voltage power supplies and PVSS.The LHC experiments will be operated as Finite State Machines (FSM) [5]. The FSM will thenensure that, for example, the high voltage state of a sub-detector is appropriate dependingon operational mode. The crate and each high voltage channel will therefore be part ofthe VELO FSM architecture (see section 5). The HV errors and alarms (see section 6) arehandled at the FSM level.2 Overview of the High Voltage Control SystemAs shown in figure 1, the control of the high voltage system starts from a PC where PVSSis installed and to which the ISEG power supplies and crate are connected. Then, the ISEGmodules control their individual channels to supply the desired voltage. Each bias voltagewill pass through the counting house cable, then the counting house patch panels. The longdistance cables distribute it to the detector patch panels onto the corresponding repeaterboard. That repeater board then supplies the bias voltage to the corresponding VELO hybrid,hence the corresponding sensor.aISEG Spezialelektronik GmbH Bautzner Landstraβe 23 D-01454 Radeberg, OT Rossendorf Deutschland.page 2The VELO High Voltage System Control Software Ref: LHCb-PUB-2009-0264 Structure of the High Voltage Control Software Date: December 1, 2009Figure 1 Overview of the high voltage system control.3 PVSS ArchitectureThe control systems that are built with PVSS are composed of communicating and inde-pendent processes. These processes are called ‘Managers’. As shown in figure 2, the mainPVSS managers are as follows. The central part is called the Event Manager (EM). It retainsall data in a volatile memory, responds to notification of data change and computes alarmconditions. Their values are held in structures called Data Points. The event manager of theVELO HV sytem is called the VELO Detector Control System High Voltage, also known as‘VEDCSHV project’. The database where non-volatile data such as system definitions, alertoccurrences and latest values are stored, is managed by the Data Manager (DM). An Oracledatabase is used for the long term storage of data point values. The visualization of thedata points values are ensured by User Interface (UI) managers such as synoptic panels,alarm screen (AES) and trend graphs (Trnd). The interconnection between individual PVSSsystems that forms a distributed system is conducted by the Distribution Manager (DIM).The list of PVSS managers provided previously is not exhaustive. Managers could be createddepending on its specific task (e.g the ISEG HV Manager is an interface to the HV modulesand crate).4 Structure of the High Voltage Control SoftwareThis section describes the structure of the HV control software (see figure 3). The VELO highvoltage system is controlled remotely via PVSS. The PVSS VELO high voltage project VEDC-SHV runs on an onlineb PC called ‘VEDCS01W’ which is located in the counting house. Thehigh voltage control software is able to control individual high voltage channels. Since theVELO has two halves, the part with +x coordinates is referred to as the A-side and the onewith −x coordinates to as the C-side, based on the LHCb coordinate systemc The VEDCSHVproject is divided into three sub-systems called ‘VELO HV’ for controlling the whole VELO,‘VELOA HV’ for controlling the A-side of the VELO, and ‘VELOC HV’ for controlling the C-side of the VELO. The PVSS ‘VEDCSHV FSM’ was developed specifically for the VELO. Thiscommunicates to the PVSS ISEG framework. The PVSS ISEG framework is developed forall CERN users of ISEG power supplies. The PVSS ISEG framework communicates with theISEG OPC Clientd. The ISEG OPC Server is provided by the ISEG company. The version ofbOnline refers to the private network which is used at the LHCb experiment area. The network is protectedbehind a strong firewall.cThe LHCb coordinate system is a right handed system with positive z running along the beam-line away fromthe interaction point and positive y ’upward’. Positive x points toward the cavern access and away from the LHCcryogenics.dThe OPC Client is the application which is interactively connected to the OPC server. It ensures the communi-cation between PVSS and the OPC server.page 3The VELO High Voltage System Control Software Ref: LHCb-PUB-2009-0265 The VELO High Voltage Finite State Machine Date: December 1, 2009Figure 2 Representation of the architecture of PVSS.the OPC Server currently used is 5.00.016e. The OPC server communicates with the powersupply module via a USB hardware adapter. This USB hardware adapter is a USB-CANinterface produced by SYSTECf.5 The VELO High Voltage Finite State MachineThe VELO FSM is constructed as a series of panels which are hierarchial and reactive.These panels allow the user to monitor and control the state of the system. The top levelpanel allows the control of all channels in the VELO. There are also panels one level downthat permit control of the channels on the A-side or C-side. A number of the functionalitiesof the HV system can be applied to sets of 8 channels, known as a ‘board’. This is a naturaldivision of the system as each power supply module controls two sets of 8 channels. Panelsare also available which monitor and control individual channels. This section provides abrief overview of the functionalities of the system. The configuration of all channels (e.g. thevoltages set, ramping speeds, software current limit) is known as a ‘recipe’. The voltagesand current limits can be set individually for each channel. The ramping speed can only beset per board. Applying this recipe starts this configuration, ramping up all channels. Therecipes can be edited from the top level panel. The recipe for all channels can be appliedfrom the top level panel. The recipe can also be applied for A-side (or C-side), a single boardor for a single channel. It is also possible to configure individual channels or whole boardsby setting the individual parameters rather than applying a recipe. There are three defaultrecipes, that all LHCb subdetectors must provide, that can be set:• GO STANDBY1: This is a first level for turning on all the channels. The voltage sup-plied to the VELO sensor at this level is 10 V.• GO STANDBY2: This is a second (higher) level for turning on all the channels. Thevoltage supplied to the VELO sensor at this level is 50 V.eThis version of the OPC server may change for future performance improvement.fSystec Automation d.o.o. Katuri 17 52220 Labin, Croatia.page 4The VELO High Voltage System Control Software Ref: LHCb-PUB-2009-0266 Alarm and Error Conditions Date: December 1, 2009Figure 3 Overview of the high voltage control software structure.• GO READY: This is the standard physics setting for the detector. The voltage suppliedto the VELO sensor at this level is 100 V. This is significantly above the depletionvoltage of all sensors. Depending on the irradiation of the VELO sensors, this voltagemay be increased.There are four types of particularly important panels in the VELO HV FSM. The top levelpanel is called VELO HV which provides control and monitoring of all HV channels in theVELO. The panels (see figure 4) that allow overall monitoring and control of all channels onthe A-side (or C-side) are VELOA HV (or VELOC HV). These panels are accessible from thetop level panel. The main panels for accessing information on one board (see figure 5) are‘VELO A HV BOARDXY’ or ‘VELO A HV BOARDXY’ (where XY is the number of the board00-05). The panels for individual channels (see figure 6) are ‘VELO A HV BOARDXY CHVW’or ‘VELO A HV BOARDXY CHVW’ (where XY is the number of the board and VW is thenumber of the channel 00-07). These panels can either be accessed from the top level, theA-side (or C-side) panels or the main board panel. The organigram in figure 7 summarisesthe information and functionalities which have been discussed here, and provides a guideas to at which level of the FSM they are available.An IV scan can also be performed. This is obtained from the top level panel, and can beperformed for either the whole VELO, A-side (or C-side), the whole board or an individualchannel. This information can then be saved. In addition, a panel is provided to performa voltage scan on selected modules for use in charge collection efficiencies analyses. Thispanel can be accessed from the Velo top level panel which is part of the Velo top PVSSproject.6 Alarm and Error ConditionsDuring the operation of the VELO, nominal operation boundary conditions have been de-fined to prevent any unexpected human mistake and to identify any abnormal behaviour ofthe sub-systems. The high voltge system characterisation and performance can be found in[6]. For the VELO HV system, the main conditions are:page 5The VELO High Voltage System Control Software Ref: LHCb-PUB-2009-0266 Alarm and Error Conditions Date: December 1, 2009Figure 4 Layout of the VELOA HV panel. The VELOC HV panel layout is similar to this panel.Figure 5 Layout of the VELOA HVBOARD01 panel. All board panel layouts are similar to thispanel.page 6The VELO High Voltage System Control Software Ref: LHCb-PUB-2009-0266 Alarm and Error Conditions Date: December 1, 2009Figure 6 Layout of the VELOA HV BOARD00 CH00 panel. All channel panels are similar to thispanel.Figure 7 Organigram showing the main VELO HV Finite State Machine structure.page 7The VELO High Voltage System Control Software Ref: LHCb-PUB-2009-0268 References Date: December 1, 2009• Implementation of the current and voltage hardware limits. Their current values areset to 240 µA and 217 V respectively.• Implementation of the current software limit for all HV channels. The value is currentlyset to 105 µA.• Implementation of a nominal ramping speed. The chosen value is approximately 1 V/s dueto the behaviour of the HV modules at low currents. Otherwise the current will trip dueto the low current limit. The nominal ramping speed may be increased to 7 V/s oncethe sensors will draw higher current.Furthermore, the HV FSM provides alarm monitoring of the general status of all HV chan-nels, modules and crate. Any problem or error in the HV system will trigger an alarm whichwill be displayed on the HV PVSS panels. The main error conditions are as follows.• ITrip error occurs when the current drawn reaches the current software limit.• ILimit error occurs when one changes the current hardware limit while using themodule.• VLimit error occurs when one changes the voltage hardware limit while using themodule.• Inhibit error occurs when the interlock signal is interrupted.• Emergency off error occurs when processes are interrupted. It causes channels toramp down and then be switched off.• AC− line power error is caused by an interruption of the normal crate power.• OPC server crash is caused by a crash of the Iseg OPC server. The server will notrespond and the process has to be restarted.The error conditions cited above may prevent the HV system to restart if uncleared.7 ConclusionThe description of the VELO high voltage control software was presented in this note. Theimplementation of its structure as a PVSS Finite State Machine was emphasized. The mainerror conditions that may occur during operation were also discussed. The VELO HV soft-ware conforms to the specification of the VELO.8 References[1] The LHCb VELO Technical Design Report, CERN-LHCC-2001-0011[2] ETM professional control PVSS, http://www.pvss.com[3] P. C. Burkimsher, JCOP Experience with a Commercial SCADA product, PVSS, 9th Inter-national Conference on Accelerator and Large Experimental Physics Control Systems,Korea, October 2003”[4] W. Salter, The LHC Experiments’ Joint Controls Project (JCOP), Computing in High En-ergy and Nuclear Physics CHEP’01, Beijing, September 2001[5] P. Y. Duval et al., Guide for ECS FSM design in LHCb sub-detectors, EDMS No: 655828[6] B. Rakotomiaramanana, C. Parkes and L. Eklund, Characterization of the VELO HighVoltage System, CERN-LHCb-2008-009page 8

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