We present an architectural concept for a first-level hardware track trigger for CMS at SLHC. The design of such a system is challenging. A primary constraint on implementation will be power consumption within the detector, in turn driven by the transmission bandwidth to offdetector electronics. We therefore emphasise the minimisation of the data flow through local filtering of track stubs on the detector. The architecture does not comprise a stand-alone track trigger, but uses muon and calorimeter trigger objects to seed track-matching within an integrated first-level system
