Detector development for the International Linear Collider (ILC) is likely to involve initial beam-tests with a triggered configuration, moving to beam-tests in a triggerless or self-triggered mode. A Trigger/Timing Logic Unit (TLU) is described which allows triggered operation, with option of smooth transition to trigger-less, data-driven mode. The unit has already been sucessfully used for a number of beam-tests

Cussans, D

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A Trigger/Timing Logic Unit for ILC Test-beamsD. CussansUniversity of Bristol, UKdavid.cussans@bristol.ac.ukAbstractDetector development for the International Linear Collider(ILC) is likely to involve initial beam-tests with a triggered con-figuration, moving to beam-tests in a triggerless or self-triggeredmode. A Trigger/Timing Logic Unit (TLU) is described whichallows triggered operation, with option of smooth transitionto trigger-less, data-driven mode. The unit has already beensucessfully used for a number of beam-tests.I. INTRODUCTIONIn the early stages of sensor development, a simple easy touse trigger system is desirable, given that at beam-tests rapidinstallation of the device under test is often needed. Trigger-ing on beam particles has traditionally been done using moduleshoused in NIM crates[2]. However, NIM crates are bulky andheavy. Moreover they are either expensive if purchased newor often in poor repair if drawn from a “loan pool”. In addi-tion it is not straightforward to expand a NIM trigger system toprovide trigger time-stamping, allowing self-triggered or trig-gerless operation of the device under test (DUT). Modern fieldprogrammable logic allows construction of a low-cost, compactand flexible trigger unit which addresses these issues.A. Design AimsAn important design aim was to place few restrictions on theuser of the TLU, whilst being as flexible as possible. The trig-ger unit should be as simple as possible, since ILC detectors willnot be triggered. It should also be low cost, to allow widespreaddistribution. Ideally, each group developing detectors should beable to have at least one TLU.B. Operating ModesThe TLU is able provide “classic” beam-test trigger system.Incoming beam triggers are combined in a user selectable com-bination and passed to one or more DUT. The TLU also keeps arecord of the arrival time of each trigger. Hence it can operate astime-to-digital converter for triggerless or self-triggered DUT.Both modes are active simultaneously, allowing triggered andtriggerless/self-triggered DUT to be mixed in the same beam-test.II. INTERFACESFour 50Ω terminated coaxial connectors accept NIM,TTLor photo-multiplier level pulses and receive a trigger for eachparticle passing through the test-beam. These four inputs arecombined to form a beam-trigger. The arrival of a beam-triggerwill cause a trigger to be output to active DUTs, unless one ormore have indicated that they are busy. Interface to the DUT isvia RJ45[1] connectors each carrying four LVDS signals. Thesignals from the TLU to the DUT are trigger and reset, the sig-nals from the DUT to the TLU are busy and DUT-clock. Thereare six DUT connectors.The FPGA is configured via the USB interface. Memory-mapped communication is used for setup and control. Then,block transfer is used to transfer time-stamps from the TLU tothe host computer.A photograph of the TLU front panel showing the variousinterfaces is shown in figure 1.Figure 1: Front Panel of the TLUA. Handshake with Device Under TestThere are three handshake modes available for communica-tion between the TLU and the DUT. The modes can be mixed,with different DUT using different handshake modes. The hand-shake modes are:• No Handshake. The TLU asserts the trigger line for afixed length of time. The busy line from the DUT is notmonitored. In this mode the TLU acts like a simple dis-criminator and coincidence/veto unit.• Trigger/Busy Handshake. The TLU asserts the triggerline connected to every DUT in the system. The TLU waitsfor each DUT to assert its busy line. When a DUT doesthis, the TLU de-asserts the corresponding trigger line andwaits for the DUT to de-assert its busy line. The TLU doesnot issue any further triggers until all the DUT drop theirbusy lines. This mode is illustrated in figure 2.420• Trigger/Busy/Trigger-Data Handshake. This mode issimilar to the Trigger/Busy handshake, but trigger infor-mation is transferred from the TLU to the DUT. When theTLU de-asserts the trigger line in response to the DUT as-serting its busy line, the DUT toggles its em DUT-clockline and the TLU will clock out trigger information on thetrigger line. Normally the trigger information is the bottomsixteen bits of the trigger counter. After the DUT is readyfor new triggers and has clocked out the trigger informa-tion, it de-asserts the busy line.This mode is illustrated infigure 3.BusyTriggerTrigger−ClockFigure 2: Simple Handshake ModeTriggerBusyTrigger−ClockD0 D1 D2 DnFigure 3: Trigger-Data Handshake ModeIII. IMPLEMENTATIONThe number of units is likely to be relatively low and theanticipated life-span of the design is modest ( 5˜ years), whichsuggests the use of a COTS FPGA module coupled to a simplecustom motherboard. Choosing a module that is supplied withUSB interface firmware and software drivers greatly reduces thedesign effort needed. The FPGA module chosen[3] uses a Cy-press EZ-USB FX2 microcontroller[4] to interface between aXilinx Spartan xc3s1000 FPGA[5] and a USB2.0 port. The im-plementation is described in more detail elsewhere[7].IV. FIRMWAREThe firmware for the FPGA was written in the VHDL. TheFPGA module vendor supplied the EX-USB FX2 microcon-troller firmware. The source code is available for a small fee.Effort was taken to ensure that the FPGA firmware can becompiled using freely down-loadable synthesis tools[6] whichallows TLU users to easily modify the firmware.A. Implementation of Asynchronous TriggerThe latency is fixed between the incoming beam-trigger andthe outgoing trigger to the DUT. In order to achieve fixed la-tency, logic asynchronous to the system clock is used. Asyn-chronous logic is prone to race conditions. To mitigate these,and make the design more straight-forward, the trigger sig-nal is de-asserted synchronously with the system clock. Fig-ure 4 shows a simplified schematic of the logic used forthe asynchronous-set/synchronous-clear of the trigger. Theasync trig in is the output of the circuitry that combines thesignals from the four beam-trigger inputs. The trig out signalis connected to the trigger output circuitry that drives each DUTinterface. The veto from fsm signal is the “or” of the fsm vetosignals from all the trigger output circuits. Figure 5 shows asimplified diagram of the finite-state-machine that controls thetrigger output circuit connected to each DUT. The trigger insignal is from the asynchronous-set/synchronous-clear logic andtrig out is the signal sent to the DUT.gndtrig_outasync_trig_in veto_from_fsm clk d q set d q set d q Figure 4: Asynchronous-set/Synchronous-clear Logic421DUT_BUSYfsm_veto<=’1’;trigger_out<=’0’;rst = ’0’WAIT_FOR_BUSY_LOWdut_busy=’0’fsm_veto<=’1’;trigger_out<=trigger_data_shift_register;dut_busy=’0’trigger_in=’0’ and dut_busy=’0’IDLEtrigger_in=’1’fsm_veto<=’0’;trigger_out<=trigger_in;dut_busy=’1’rst IDLEIDLEWAIT_FOR_BUSY_HIGHfsm_veto <=’1’;trigger_out<=’1’;dut_busy=’1’Figure 5: Finite State Machine for TLU Trigger OutputsB. Trigger LatencyWith the version of the firmware in use at the time of writ-ing, the latency between a trigger of fixed amplitude arriving atthe TLU and a trigger being issued by the TLU to the DUT is27.3 ± 1.5ns. The error quoted is the spread between differ-ent DUT outputs and the variation anticipated over the expectedtemperature range. At a fixed temperature for a given DUT out-put the variation in latency (the timing jitter) is much smaller.The measured latency jitter is 24 ± 5ps. The fixed-thresholddiscriminator used is subject to timing walk for pulses of vary-ing amplitude. The discriminator contributes in the region of14ns to the total latency. With a faster discriminator and a cus-tom FPGA layout rather than a COTS module a total latency ofunder 10ns would be achievable.C. Trigger TimestampingCurrently the firmware is configured to store a 64-bit time-stamp for each trigger issued. By default the time-stamp res-olution is 20.83ns, which is the period of the internal crystaloscillator. However, the TLU can accept an external clock of upto 100MHz. In this case, the time-stamp resolution is the periodof the external clock. The time-stamps are stored in memoryinside the FPGA, limiting the number of time-stamps to 4096.However, the FPGA module used has a 8MByte of low-latencySRAM and it is planned to modify the firmware to store time-stamps in this external memory. This would allow up to 512ktime-stamps to be stored. Using delay-locked-loop (DLL) fre-quency multipliers inside the FPGA together with double-edgeclocking it is possible to improve the time-stamp resolution toone-eigth of the clock period. These technique have been usedin firmware designed for the CMS calorimeter trigger[8] and inthe TLU will allow a time-stamp resolution of approximately2.5ns.V. CONCLUSIONSThe ready availability of programmable logic devices hasallowed the construction of a simple, yet flexible, trigger sys-tem for use in ILC beam-tests. The unit is lower cost, morecompact and more flexible than a system constructed from tra-ditional NIM units. The TLU was developed as part of ILCvertex-detector development, but could also be used for otherbeam-tests.REFERENCES[1] Telephone terminal equipment - Technical requirementsfor connection of terminal equipment to the telephone net-work. Telecommunications Industry Association (TIA) re-port, ANSI/TIA-968-A, 2002.[2] Standard NIM Instrumentation System. U.S. NIM Com-mittee, U.S. Department of Energy Report, DOE/ER-0457T, 1990.[3] The ZestSC1 USB FPGA Board. Orange Tree Technolo-gies Ltd Harwell Innovation Centre, 173 Curie Avenue,Didcot, OX11 0QG, UK, 2006.[4] EZ-USB FX2LP(TM) - Low Power (Bus Powered) Pro-grammable MCU for bus power peripherals. Cypress Inc,198 Champion Ct. San Jose, CA 95134 USA, 2006.[5] Spartan-3 FPGA Family Data Sheet DS099. Xilinx Inc,2100 Logic Drive San Jose, CA 95124-3400, USA, 2006.[6] ISE WebPACK 9.2i, Xilinx Inc.[7] Description of the JRA1 Trigger Logic Unit (TLU). D.Cussans, EUDET-Memo-2007-02, 2007.[8] The Design of a Flexible Global Calorimeter Trigger Sys-tem for the Compact Muon Solenoid Experiment, J. J.Brooke, D. G. Cussans, R. J. E. Frazier, S. B. Galagedera,G. P. Heath, B. J. Huckvale, S. J. Nash, D. M. Newbold, A.A. Shah. Manuscript submitted for publication in Journalof Instrumentation, 2007.422

A Trigger/Timing Logic Unit for ILC Test-beams

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