We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 m fullydepleted- SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5mm2 consisting of 20 x 20 um2 pixels have been designed and manufactured. Performance tests with a laser light illumination and a . ray radioactive source indicate successful operation of the detector. We also brie y discuss the back gate effect as well as the simulation study

Arai, Y

Fukuda, K

Hara, K

Hazumi, M

Ida, J

Ikeda, H

Ikegami, Y

Ishino, H

Ishino, Hirokazu

Kawasaki, T

Kohriki, T

Komatsubara, H

Martin, E

Miyake, H

Ohno, M

Tajima, H

Tajima, O

Terada, S

Tsuboyama, T

Unno, Y

Ushiroda, Y

Varner, G

We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 {micro}m fully-depleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5 mm{sup 2} consisting of 20 x 20 {micro}m{sup 2} pixels have been designed and manufactured. Performance tests with a laser light illumination and a {beta} ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study

Arai, Y.

Hazumi, M.

Ikegami, Y.

Kohriki, T.

Tajima, O.

Terada, S.

Tsuboyama, T.

Unno, Y.

Ushiroda, Y.

Ikeda, H.

Hara, K.

Ishino, H.

Kawasaki, T.

Miyake, H.

Martin, E.

Varner, G.

Tajima, H.

Ohno, M.

Fukuda, K.

Komatsubara, H.

Ida, J.

UNT Digital Library

Work supported in part by US Department of Energy contract DE-AC02-76SF00515Development of a CMOS SOI Pixel DetectorY. Araia, M. Hazumia, Y. Ikegamia, T. Kohrikia, O. Tajimaa, S. Teradaa T. Tsuboyamaa, Y. Unnoa,Y. Ushirodaa, H. Ikedab, K. Harac, H. Ishinod, T. Kawasakie, H. Miyakef, E. Marting, G. VarnergH. Tajimah M. Ohnoi, K. Fukudai, H. Komatsubarai, J. Idaifor the SOIPIX groupa IPNS, High Energy Accelerator Research Organization (KEK), Ibaraki 305-0801, Japanb ISAS, Japan Aerospace Exploration Agency (JAXA), Kanagawa 229-8510, Japanc Institute of Pure and Applied Science, University of Tsukuba, Ibaraki 305-8571, Japand Department of Physics, Tokyo Institute of Technology, Tokyo 152-8550, Japane Graduate School of Science and Technology, Niigata University, Niigata 950-2181, Japanf Department of Physics, Osaka University, Osaka 560-0043, Japang Department of Physics and Astronomy, University of Hawaii, Honolulu, HI 86822, USAh Stanford Linear Accelerator Center, Stanford, CA 94307-4349, USAi Oki Electric Industory Co. Ltd., Tokyo 192-8550, Japan  		 ﬁﬀﬂﬁﬃAbstractWe have developed a monolithic radiation pixel detector usingsilicon on insulator (SOI) with a commercial 0.15  m fully-depleted-SOI technology and a Czochralski high resistivity sil-icon substrate in place of a handle wafer. The SOI TEG (TestElement Group) chips with a size of !"$#%&!"$# mm ' consistingof !)(*%+!,(- m'pixels have been designed and manufactured.Performance tests with a laser light illumination and a . ray ra-dioactive source indicate successful operation of the detector.We also briefly discuss the back gate effect as well as the simu-lation study.I. INTRODUCTIONA monolithic radiation pixel detector with the SOI technol-ogy is one of the position sensitive detectors that are able toovercome the difficulties in decreasing the pixel size and thick-ness, and the bump bonding employed by a hybrid pixel detec-tor. The SOI pixel detector consists of a monolithic Silicon layer(handle wafer) covered with a insulating SiO'layer (Buried Ox-ide, BOX), and a thin Silicon film (device layer) over the BOX,in which a readout LSI is formed. The handle wafer is used fora radiation sensor with a matrix of depleted diodes directly con-nected to the LSI through a hole in the BOX. The SOI structureenables us to use two different types of silicon, i.e., the high re-sistivity silicon handle wafer for the radiation detection and thelow resistivity silicon film for the readout electronics utilizingCMOS transistors.Transistors formed on the SOI wafer can operate with higherspeed and lower power consumption compared with the con-ventional bulk CMOS processes because of less parasitic ca-pacitance [1]. Moreover, the SOI transistors are free from thelatch-ups since individual transistors are completely separatedby the BOX layer and have no PNPN parasitic structure. Thethin device layer is insensitive to Single Event Upsets and Tran-sients [2] due to its small energy deposit by ionizing radiations.Those SOI characteristics can satisfy the requirements of furtherimprovement of the spatial resolution and radiation hardness im-posed by future particle physics, astrophysics and medicine.We have developed the SOI pixel detector in collaborationwith OKI Electric Industry Co. Ltd. [3]. The basic technologyof OKI’s fully-depleted 0.15  m CMOS SOI process [4] is em-ployed. Additional processing steps for the implants to the han-dle wafer and contacts to it have also been developed. Figure 1shows a cross-section of the SOI pixel detector.Figure 1: Cross-section of the SOI pixel detector.II. THE SOI PROCESSThe SOI wafer is provided by SOITEC which employs thesmart-cut procedure for the production. The wafer consists ofa high resistive Cz silicon handle wafer ( /10 k 23m), a BOXlayer with a thickness of 200 nm on the substrate and a p-type50 nm thin Cz silicon film on the top in which transistors areformed. Since there is no original type assignment of the handlewafer and a possibility that the type could change during pro-cessing due to the thermal donor generation [5], we fabricatedtwo kinds of TEG chips for p-type and n-type handle wafers.SLAC-PUB-13374August 2008Contributed to the 12th Workshop on Electronics for LHC and Future Experiments (LECC 2006), 09/25-29/2006, Valencia, SpainThe implantation of p+ and n+ to the handle wafer and theformation of transistor drain and source implantation on the sil-icon film are performed simultaneously with the carrier densityof about 04( '65 cm 78 after opening holes in the BOX. This proce-dure can decrease the number of masks and process steps, andtherefore costs. The implantation in the handle wafer is con-nected to a metal contact through the hole in the BOX. Threeto five metal layers are formed on the silicon film for the circuitformation. Three different types of transistors are fabricated inthe SOI process: high voltage transistors for I/O buffers, highthreshold transistors utilized for normal logic and low thresholdtransistors used for high speed circuit. The pixel readout circuitemploys the high threshold transistors with body ties.The handle wafer having an original thickness of 650  mis thinned to 350  m, and its backside is plated with a 200 nmaluminum film. The detector bias can be applied from either thealuminum backside or pads on the top, both are connected to ann+ implant HV ring.III. DIODE TEGTo determine the handle wafer type prior to process pixelTEG chip, we fabricated diode TEG chips having p+ and n+ im-plant in the handle wafer. Figure 2 shows a TEM picture of thecross section of the p+ implanted diode TEG and metal contactsto the first metal layer. The measured sheet resistance of p+ (n+)implant is 136 (33) 2 /squre. The ("90;:<%=("90;: m ' contact resis-tance is measured to be 218 (87) for p+ (n+) implant. We per-form the I-V measurements for both p+ and n- implanted diodeTEG. Figure 3 shows the curves of the diode TEG between p+implant and the backside, indicating the diode characteristic andtherefore the ’n’ type handle wafer. We also measure the handlewafer resistivity with a four point probe to be 700 23m, corre-sponding to the carrier density about :%>0;(@? ' cm 7A8 .Figure 2: TEM picture of the cross section of the p+ implanted diodeTEG and metal contacts to the first metal layer.Figure 3: Measured I-V curve between p+ implant and the backside.IV. PIXEL TEGThe !" #B%ﬂ!" # mm ' pixel TEG chip consists of a CD!E%ﬂCF! ma-trix of pixels with a size of !,(G%H!,(< m'. Figure 4 shows a pic-ture of one pixel cell, which is composed of four #" IJ%K#" IL m 'octagonal p+ implants and a storage capacitor of 0;(F( fF. Thepixel center is opened for a light illumination test. The accumu-lated charge is read out using correlated double sampling.Figure 4: Picture of one pixel cell which is composed of four M,N OQPM,N OSR m T octagonal p+ implants and a storage capacitor of UWV;V fF. Thepixel center is opened for a light illumination test.Figure 5 shows a I-V measured curve of the pixel TEG,where the bias voltage is applied from the backside Aluminumcover. The same curve is obtained by applying the bias to theHV ring pad. The breakdown happens when more than 98 V isapplied, where the depletion thickness is about 140  m. Usingan infrared camera we find that the breakdown is caused by ahot spot around the corner of the bias ring. This can be curedby smoothing the corner and moving the ring inward. However,there is a much lower bias voltage limit for the proper operationof the pixel TEG readout due to the back gate effect describedin the next section.Figure 5: I-V measured curve of the pixel TEG.We take a picture by illuminating red laser light (670 nmwavelength) with a plastic mask placed in front of the pixelTEG. We apply the detector bias of 10 V and expose it for 7  s.Figure 6 shows an image obtained. From the size of the pixelwindow and the laser light intensity, we estimate the number ofphotons detected in the white part of the image to be !X%Y0;(Z ;we expect 400 mV output signal height with 8 fF pixel capac-itance. The measured signal amplitude is consistent with theexpectation.We also irradiate . rays using a [5Sr source. Figure 7 showsan oscilloscope image of the pixel TEG output. The step in thepicture indicates the . ray signal. The size is measured to be70 mV, which is consistent with the estimated collected chargeof 0.6 fC (3500e) with the depletion thickness of 44  m and thepixel capacitance of 8 fF.Figure 6: Picture taken using the pixel TEG with a red laser.Figure 7: \ ray signal in the oscilloscope image of the pixel TEG out-put.V. BACK GATE EFFECTThe transistors on the top Si film is affected by the potentiallevel in the handle wafer, i.e. the transistor threshold voltagedepends on the bias voltage applied to the handle wafer. Fig-ure 8 shows measured threshold voltages of the three differenttypes of transistors as a function of the bias voltage. The de-pendence is clearly seen, and the readout circuit is expected tostop its function with bias voltage more than 10 V. We confirmthis by observing the signal output of the I/O buffer. Figure 9shows an oscilloscope image of the input and output signals ofthe I/O buffer. The output signal shape starts deviating when thebias voltage exceeds 15V. This behavior is also confirmed witha SPICE simulation.Using a 3D TCAD simulation [6], we find that the back gateeffect of an NMOS transistor can be reduced by implanting p+in the handle wafer near the transistor position. We are optimiz-ing the design and layout of the implant using the simulation.VI. SUMMARYWe have started development of the SOI pixel detector us-ing a commercial OKI 0.15  m SOI process and SOITEC wafer.We identify the handle wafer type as ’n’ and find that its resis-tivity is satisfactory for the radiation detection. The pixel TEGhas been fabricated and tested. Photo images are successfullytaken and . ray signals are clearly detected. We find that theback gate effect can be removed by placing implantation nearthe transistors. The distance and shape of the implant is beingoptimized using the TCAD simulation.Figure 8: Measured threshold voltage (Vth) as a function of the biasvoltage applied to the backside (Vback) for NMOS and PMOS transis-tors of three different types.Figure 9: Oscilloscope image of the input and output signal of the I/Obuffer. The output signal deviation becomes large as the bias voltageincreases.REFERENCES[1] X. Llopart et al., IEEE Trans. Nucl. Sci. Vol. 49, (2002)2279-2283.[2] A. Makihara et al., IEEE Trans. Nucl. Sci. Vol. 52, (2005)2524-2530.[3] SOI Pixel detector R&D, ]^^D_E`baDa)cdegfhFfSe6i)_jak_clihmn^aolp .[4] K. Morikawa and M. Mitarashi, OKI Technical Review Is-sue 196, Vol. 70, No. 4 (2003) 60-63, ]^^D_E`6aa,qqqSe6lFfApem)lnraDh,saDlF^catnuva,dl)qFswFlxFdoa)lF^Dcjy@t4uvyzt;{	e|_d} .[5] J. Hakonen et al., Nucl. Instr. and Meth. A552, (2005) 43-48.[6] ENEXSS simulator, ]^^F_E`baa,qDqqEe~rpnF]lypncem)l	egi)_jah)sjwjpo]aolw,^Ap,lksaDhksjh)oDo .

Development of a CMOS SOI Pixel Detector

CERN Document Server

Development of a CMOS SOI Pixel DetectorY. Araia, M. Hazumia, Y. Ikegamia, T. Kohrikia, O. Tajimaa, S. Teradaa T. Tsuboyamaa, Y. Unnoa,Y. Ushirodaa, H. Ikedab, K. Harac, H. Ishinod, T. Kawasakie, H. Miyakef, E. Marting, G. VarnergH. Tajimah M. Ohnoi, K. Fukudai, H. Komatsubarai, J. Idaifor the SOIPIX groupa IPNS, High Energy Accelerator Research Organization (KEK), Ibaraki 305-0801, Japanb ISAS, Japan Aerospace Exploration Agency (JAXA), Kanagawa 229-8510, Japanc Institute of Pure and Applied Science, University of Tsukuba, Ibaraki 305-8571, Japand Department of Physics, Tokyo Institute of Technology, Tokyo 152-8550, Japane Graduate School of Science and Technology, Niigata University, Niigata 950-2181, Japanf Department of Physics, Osaka University, Osaka 560-0043, Japang Department of Physics and Astronomy, University of Hawaii, Honolulu, HI 86822, USAh Stanford Linear Accelerator Center, Stanford, CA 94307-4349, USAi Oki Electric Industory Co. Ltd., Tokyo 192-8550, Japan  		 ﬁﬀﬂﬁﬃAbstractWe have developed a monolithic radiation pixel detector usingsilicon on insulator (SOI) with a commercial 0.15  m fully-depleted-SOI technology and a Czochralski high resistivity sil-icon substrate in place of a handle wafer. The SOI TEG (TestElement Group) chips with a size of !"$#%&!"$# mm ' consistingof !)(*%+!,(- m'pixels have been designed and manufactured.Performance tests with a laser light illumination and a . ray ra-dioactive source indicate successful operation of the detector.We also briefly discuss the back gate effect as well as the simu-lation study.I. INTRODUCTIONA monolithic radiation pixel detector with the SOI technol-ogy is one of the position sensitive detectors that are able toovercome the difficulties in decreasing the pixel size and thick-ness, and the bump bonding employed by a hybrid pixel detec-tor. The SOI pixel detector consists of a monolithic Silicon layer(handle wafer) covered with a insulating SiO'layer (Buried Ox-ide, BOX), and a thin Silicon film (device layer) over the BOX,in which a readout LSI is formed. The handle wafer is used fora radiation sensor with a matrix of depleted diodes directly con-nected to the LSI through a hole in the BOX. The SOI structureenables us to use two different types of silicon, i.e., the high re-sistivity silicon handle wafer for the radiation detection and thelow resistivity silicon film for the readout electronics utilizingCMOS transistors.Transistors formed on the SOI wafer can operate with higherspeed and lower power consumption compared with the con-ventional bulk CMOS processes because of less parasitic ca-pacitance [1]. Moreover, the SOI transistors are free from thelatch-ups since individual transistors are completely separatedby the BOX layer and have no PNPN parasitic structure. Thethin device layer is insensitive to Single Event Upsets and Tran-sients [2] due to its small energy deposit by ionizing radiations.Those SOI characteristics can satisfy the requirements of furtherimprovement of the spatial resolution and radiation hardness im-posed by future particle physics, astrophysics and medicine.We have developed the SOI pixel detector in collaborationwith OKI Electric Industry Co. Ltd. [3]. The basic technologyof OKI’s fully-depleted 0.15  m CMOS SOI process [4] is em-ployed. Additional processing steps for the implants to the han-dle wafer and contacts to it have also been developed. Figure 1shows a cross-section of the SOI pixel detector.Figure 1: Cross-section of the SOI pixel detector.II. THE SOI PROCESSThe SOI wafer is provided by SOITEC which employs thesmart-cut procedure for the production. The wafer consists ofa high resistive Cz silicon handle wafer ( /10 k 23m), a BOXlayer with a thickness of 200 nm on the substrate and a p-type50 nm thin Cz silicon film on the top in which transistors areformed. Since there is no original type assignment of the handlewafer and a possibility that the type could change during pro-cessing due to the thermal donor generation [5], we fabricatedtwo kinds of TEG chips for p-type and n-type handle wafers.2630123456789The implantation of p+ and n+ to the handle wafer and theformation of transistor drain and source implantation on the sil-icon film are performed simultaneously with the carrier densityof about 04( '65 cm 78 after opening holes in the BOX. This proce-dure can decrease the number of masks and process steps, andtherefore costs. The implantation in the handle wafer is con-nected to a metal contact through the hole in the BOX. Threeto five metal layers are formed on the silicon film for the circuitformation. Three different types of transistors are fabricated inthe SOI process: high voltage transistors for I/O buffers, highthreshold transistors utilized for normal logic and low thresholdtransistors used for high speed circuit. The pixel readout circuitemploys the high threshold transistors with body ties.The handle wafer having an original thickness of 650  mis thinned to 350  m, and its backside is plated with a 200 nmaluminum film. The detector bias can be applied from either thealuminum backside or pads on the top, both are connected to ann+ implant HV ring.III. DIODE TEGTo determine the handle wafer type prior to process pixelTEG chip, we fabricated diode TEG chips having p+ and n+ im-plant in the handle wafer. Figure 2 shows a TEM picture of thecross section of the p+ implanted diode TEG and metal contactsto the first metal layer. The measured sheet resistance of p+ (n+)implant is 136 (33) 2 /squre. The ("90;:<%=("90;: m ' contact resis-tance is measured to be 218 (87) for p+ (n+) implant. We per-form the I-V measurements for both p+ and n- implanted diodeTEG. Figure 3 shows the curves of the diode TEG between p+implant and the backside, indicating the diode characteristic andtherefore the ’n’ type handle wafer. We also measure the handlewafer resistivity with a four point probe to be 700 23m, corre-sponding to the carrier density about :%>0;(@? ' cm 7A8 .Figure 2: TEM picture of the cross section of the p+ implanted diodeTEG and metal contacts to the first metal layer.Figure 3: Measured I-V curve between p+ implant and the backside.IV. PIXEL TEGThe !" #B%ﬂ!" # mm ' pixel TEG chip consists of a CD!E%ﬂCF! ma-trix of pixels with a size of !,(G%H!,(< m'. Figure 4 shows a pic-ture of one pixel cell, which is composed of four #" IJ%K#" IL m 'octagonal p+ implants and a storage capacitor of 0;(F( fF. Thepixel center is opened for a light illumination test. The accumu-lated charge is read out using correlated double sampling.Figure 4: Picture of one pixel cell which is composed of four M,N OQPM,N OSR m T octagonal p+ implants and a storage capacitor of UWV;V fF. Thepixel center is opened for a light illumination test.2640123456789Figure 5 shows a I-V measured curve of the pixel TEG,where the bias voltage is applied from the backside Aluminumcover. The same curve is obtained by applying the bias to theHV ring pad. The breakdown happens when more than 98 V isapplied, where the depletion thickness is about 140  m. Usingan infrared camera we find that the breakdown is caused by ahot spot around the corner of the bias ring. This can be curedby smoothing the corner and moving the ring inward. However,there is a much lower bias voltage limit for the proper operationof the pixel TEG readout due to the back gate effect describedin the next section.Figure 5: I-V measured curve of the pixel TEG.We take a picture by illuminating red laser light (670 nmwavelength) with a plastic mask placed in front of the pixelTEG. We apply the detector bias of 10 V and expose it for 7  s.Figure 6 shows an image obtained. From the size of the pixelwindow and the laser light intensity, we estimate the number ofphotons detected in the white part of the image to be !X%Y0;(Z ;we expect 400 mV output signal height with 8 fF pixel capac-itance. The measured signal amplitude is consistent with theexpectation.We also irradiate . rays using a [5Sr source. Figure 7 showsan oscilloscope image of the pixel TEG output. The step in thepicture indicates the . ray signal. The size is measured to be70 mV, which is consistent with the estimated collected chargeof 0.6 fC (3500e) with the depletion thickness of 44  m and thepixel capacitance of 8 fF.Figure 6: Picture taken using the pixel TEG with a red laser.Figure 7: \ ray signal in the oscilloscope image of the pixel TEG out-put.V. BACK GATE EFFECTThe transistors on the top Si film is affected by the potentiallevel in the handle wafer, i.e. the transistor threshold voltagedepends on the bias voltage applied to the handle wafer. Fig-ure 8 shows measured threshold voltages of the three differenttypes of transistors as a function of the bias voltage. The de-pendence is clearly seen, and the readout circuit is expected tostop its function with bias voltage more than 10 V. We confirm2650123456789this by observing the signal output of the I/O buffer. Figure 9shows an oscilloscope image of the input and output signals ofthe I/O buffer. The output signal shape starts deviating when thebias voltage exceeds 15V. This behavior is also confirmed witha SPICE simulation.Using a 3D TCAD simulation [6], we find that the back gateeffect of an NMOS transistor can be reduced by implanting p+in the handle wafer near the transistor position. We are optimiz-ing the design and layout of the implant using the simulation.VI. SUMMARYWe have started development of the SOI pixel detector us-ing a commercial OKI 0.15  m SOI process and SOITEC wafer.We identify the handle wafer type as ’n’ and find that its resis-tivity is satisfactory for the radiation detection. The pixel TEGhas been fabricated and tested. Photo images are successfullytaken and . ray signals are clearly detected. We find that theback gate effect can be removed by placing implantation nearthe transistors. The distance and shape of the implant is beingoptimized using the TCAD simulation.Figure 8: Measured threshold voltage (Vth) as a function of the biasvoltage applied to the backside (Vback) for NMOS and PMOS transis-tors of three different types.Figure 9: Oscilloscope image of the input and output signal of the I/Obuffer. The output signal deviation becomes large as the bias voltageincreases.REFERENCES[1] X. Llopart et al., IEEE Trans. Nucl. Sci. Vol. 49, (2002)2279-2283.[2] A. Makihara et al., IEEE Trans. Nucl. Sci. Vol. 52, (2005)2524-2530.[3] SOI Pixel detector R&D, ]^^D_E`baDa)cdegfhFfSe6i)_jak_clihmn^aolp .[4] K. Morikawa and M. Mitarashi, OKI Technical Review Is-sue 196, Vol. 70, No. 4 (2003) 60-63, ]^^D_E`6aa,qqqSe6lFfApem)lnraDh,saDlF^catnuva,dl)qFswFlxFdoa)lF^Dcjy@t4uvyzt;{	e|_d} .[5] J. Hakonen et al., Nucl. Instr. and Meth. A552, (2005) 43-48.[6] ENEXSS simulator, ]^^F_E`baa,qDqqEe~rpnF]lypncem)l	egi)_jah)sjwjpo]aolw,^Ap,lksaDhksjh)oDo .2660123456789

Development of a CMOS SOI pixel detector

https://digital.library.unt.edu/ark:/67531/metadc893959/m2/1/high_res_d/937201.pdf

Development of a CMOS SOI pixel detector

Abstract

Similar works

Full text

Available Versions

UNT Digital Library

CERN Document Server