Deleuran, Alexander N.

Jørgensen, Ivan Harald Holger

Lindbjerg, Nicklas

Llimos Muntal, Pere

Pedersen, Martin K.

Alexander N. Deleuran

Nicklas Lindbjerg

Martin K. Pedersen

Pere Llimos Muntal

Ivan H.H. Jorgensen

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A capacitor-free, fast transient response linear voltage regulator in a 180nm CMOS

A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration. A current step load from 0-50 mA with a rise time of 1 µs results in an undershoot in the output voltage of 140 mV for a period of 39 ns. The regulator sources up to 50 mA current load

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Downloaded from orbit.dtu.dk on: Dec 21, 2017A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOSDeleuran, Alexander N.; Lindbjerg, Nicklas; Pedersen, Martin K. ; Llimos Muntal, Pere; Jørgensen, IvanHarald HolgerPublished in:Proceedings of NORCAS 2015Link to article, DOI:10.1109/NORCHIP.2015.7364358Publication date:2015Document VersionPeer reviewed versionLink back to DTU OrbitCitation (APA):Deleuran, A. N., Lindbjerg, N., Pedersen, M. K., Llimos Muntal, P., & Jørgensen, I. H. H. (2015). A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOS. In Proceedings of NORCAS 2015IEEE. DOI: 10.1109/NORCHIP.2015.7364358A Capacitor-Free, Fast Transient Response LinearVoltage Regulator In a 180nm CMOSAlexander N. Deleuran, Nicklas Lindbjerg, Martin K. Pedersen, Pere Llimo´s Muntal and Ivan H.H. JørgensenDepartment of Electrical EngineeringTechnical University of Denmark, Kgs. Lyngby, Denmarks130382@student.dtu.dk, s130381@student.dtu.dk, s125187@student.dtu.dk, plmu@elektro.dtu.dk, ihhj@elektro.dtu.dkSlowFast 		 Fig. 1: Functional diagram of the proposed linear voltageregulatorampliﬁer. In [3] the transient performance is enhanced by anassisting ampliﬁer and the DC output level is stabilized by alow bandwidth ampliﬁer in a parallel control loop.The new design proposed in this work is based on a princi-ple similar to [3], employing two control loops and an NMOSpass transistor conﬁgured as a source follower (SF). Referto Fig. 1 for the circuit diagram of the proposed regulator.The design speciﬁcations target the following parameters. Theregulator is supplied by voltage of 3.3 V and an outputs avoltage of 1.8 V. The regulator can source an IL of 0-50 mAwhich can be stepped with a 1 μs rise -and fall time. Theoutput voltage undershoots less than 200 mV during currentstep load and the circuit consumes less than 100 μA withoutload. A CL of 1 pF or less will not cause ripple on the output.The design is intended for small products like hearing aids.All transistors in the circuit are 5 V MOSFETs.II. CIRCUIT DESCRIPTIONThe fast loop consists of a common source (CS) ampliﬁer,Q2 and Q3, driving the pass transistor Q1. The current sourceQ3 is controlled by the slow loop comprising the operationalampliﬁer. The proposed design does not contain any large pas-sive devices and has a low count of transistors. Consequentlythe simplicity allows for easy and space efﬁcient implementa-tion, yet demonstrating good performance. CL depicts the loadcapacitance The following sections describe the two controlloops in detail. A full circuit diagram is depicted on Fig. 2.Abstract—A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 μm CMOS process. The design has a low component count and is tailored for system-on-chip integration. A current step load from 0-50 mA with a rise time of 1 μs results in an undershoot in the output voltage of 140 mV for a period of 39 ns. The regulator sources up to 50 mA current load.I. INTRODUCTIONIn contemporary low power CMOS integrated circuits, multiple supply voltages are often a necessity for optimizing chip area and power efﬁciency. Linear regulators excel at providing low output noise and less electromagnetic emission compared to switching mode regulators. Opposed to switching regulators, linear regulators do not require external inductors and are generally less space consuming. Despite a lower power efﬁciency, linear regulators can be designed to draw a noticeably low quiescent current, i.e. the sum of bias currents during unloaded conditions, since these designs do not depend on a minimum duty cycle. This is advantageous for handheld systems where most energy is consumed in stand-by mode [1].Due to a ﬁnite bandwidth of linear regulators, conventional designs require a high value buffer capacitor, frequently situ-ated off-chip [2]. In portable devices with strict requirements on space consumption, such as hearing aids or cell phones, usage of discrete components must be minimized. This has lead to the development of numerous capacitor-free regulator topologies [3]–[5]. The external capacitor ensures stability and acts as a supply for the frequency components of the current load, IL, outside the bandwidth of the regulator. With fast changing current loads an exclusion of the capacitor will lead to large voltage drops on the output and a longer duration of transient recovery, i.e. rise time, TR.One approach of avoiding this large capacitor is by emu-lating the capacitance using an internal operational ampliﬁer-based active circuit as done in [4]. However, the design is rather complex and utilizes a low dropout methodology with a PMOS pass transistor. Considering the lower charge carrier mobility in most PMOS devices, more area is consumed compared to an NMOS with the same drain current. This increases the gate capacitance and leads to a longer TR. Another approach is to increase the bandwidth of the control loop to a level where the regulator is able to compensate for the fast changing current loads [3]. This is achieved by controlling the pass transistor with a simple single stage error		  OperationalAmplifierCSStageSFStageFig. 2: Full schematic of the proposed linear regulatorA. Fast LoopBy assuming the fast loop constitutes an underdampedsystem, the gain bandwidth product (GBWP) of the open loopgain will be inversely proportional to TR. The open loop startsat the gate of Q2 and ends at the source of Q1 Based on theformer assumption, an uncompensated error ampliﬁer with amaximized GBWP/ID can be employed in order to exploitmost of the quiescent current for control speed. ID is the draincurrent, here spent in the gain stage of the ampliﬁer.AOL(s) =(gm2RcsR′LR′L + 1/gm1) (1 + sωz)(1 + sωp1)(1 + sωp2) (1)where R′L = (R1 +R2)||rds1||(1/gs1)ωp1 =(1/Rcs)(gm1 + 1/R′L)C ′L/Rcs + C1(gm1 + 1/Rcs) + Cgs1/R′L(2)ωp2 =C ′L/Rcs + C1(gm1 + 1/Rcs) + Cgs1/R′LCgs1C ′L + C1(Cgs1 + C′L)(3)ωz = gm1/Cgs1 (4)The open loop transfer function, AOL(s), is described in(1) where Rcs is the output resistance of the CS stage, C ′Lis CL plus the source-bulk capacitance of Q1, Cgs1 is thegate-source capacitance and C1 is the gate-bulk and gate-draincapacitance of Q1. rds1 is the output resistance and gs1 is thebody transconductance of Q1.Since the CS stage delivers the gain of fast loop thetransconductance of Q2, gm2, must be maximized to achievethe greatest GBWP. Correspondingly R1 and R2 are usedto decrease the gate voltage of Q2 and thereby drive it intomoderate inversion for a higher gm. These resistors also biasQ1. The optimum current distribution in the CS and SF, thatresulted in the shortest TR, was found empirically. The gate-source voltage of Q1, Vgs1, becomes considerably large atmaximum IL. The body effect additionally increases Vgs1, soQ1 must have a very high W/L to keep Q3 in saturation. Thisvast device area introduces substantial parasitic capacitancesin Q1 which will dominate the frequency response of thefast loop in terms of C1 and Cgs1. To minimize TR, thedimensions of Q1 must therefore be kept as low as the effectivevoltage, Veff , of Q3 allows it. At maximum IL the drain-source voltage of Q3 will be at its minimum and will be thelimiting factor when choosing the supply voltage. However, if aslightly lower voltage domain is available, it can be connectedto the drain of Q1. In that way the power dissipated in Q1can be signiﬁcantly reduced without sacriﬁcing performance.Another limiting factor is the load capacitance. As seen in(2) and (3), greater values of CL will push the poles downin frequency and potentially closer together, and therefore atsome point compromise the system stability. This signiﬁcantlydetermines the maximum amount of devices that the linearregulator can supply.The loop gain of the fast loop is deﬁned as L(s) =AOL(s)R2R1. When current step loads are applied, ringing canoccur on the output of the regulator due to insufﬁcient phasemargin of the loop response. Therefore it is desirable to keepthe phase margin of L(s) above 75 degrees at maximumexpected load capacitance.B. Slow LoopThe role of the slow loop is to control the gate voltage ofQ3 and thereby stabilize the DC level at Vout. The well knownMiller compensated, two stage operational ampliﬁer (opamp)has been utilized for this function. Transistor Q11 to Q18 andCC constitute the opamp. The slow loop starts at the gate ofQ12, then goes through the opamp, from gate to the source ofQ3 and then from the gate to the source of Q1.In order not to degrade the frequency response of the fastloop, this opamp has a unity gain frequency approximatelytwo decades below the one of the fast loop; wherefore theopamp does only require a minimal bias current. When greaterTime [s]0 1 2 3 4 5 6 7Voltage [V]1.61.71.81.92Current [mA]0204060Schematic - CL=0pFLayout - CL=0pFLayout - CL=20pFLoad currentFig. 4: Transient response with closed slow and fast loop, simulation with and without extracted parasiticsFrequency [Hz]101 102 103 104 105 106 107 108 109 1010Gain [dB]-40-20020406080 OpampCSSF(a) Frequency response of the operational ampliﬁer, the commonsource stage (Q3 isolated from the opamp) and the source followerstage, all without extracted parasitics. CL = 0 and IL = 0Frequency [Hz]104 105 106 107 108 109Gain [dB]-50-25025GainPhase Phase [°]0100200300400IL=0mA, CL=0pFIL=0mA, CL=20pFIL=50mA, CL=0pFIL=50mA, CL=20pF(b) Transfer function of L(s) (Q3 isolated from the opamp), with andwithout capacitive and current load, all without extracted parasiticsFig. 3: Simulation results of the proposed linear regulatorsteps in IL occur the opamp must be able to drive the gateof Q3 without slewing the transient. Therefore, the commonsource stage of the opamp must provide a sufﬁciently largedrain current of Q16, ID16. The required ID16 can be reducedby choosing a lower W/L for Q3 to reduce the parasiticcapacitance related to the gate. A shorter channel length of Q3will reduce Rcs and thereby decrease ωp1 which will lead to alower GBWP. Chosing W3/L3 is consequently a compromisebetween GBWP of the CS stage, Vgs of Q3, which also dictatesW1/L1, and ﬁnally the necessary ID16 to reduce slewing.The design compromises of the slow and fast loop dis-cussed above lead to the device dimensions and drain currentspresented in Table I. A value of 300 fF was chosen for CC .III. SIMULATION RESULTSThe proposed capacitor-free linear voltage regulator hasbeen implemented on schematic and layout level in a 0.18μm CMOS process. The presented results are from the typicaltemperature and process corner. The most advantageous biascurrent distribution has been ﬁne tuned by simulation to yieldthe fastest TR. As a result, 82.2 μA is distributed to the CSstage, 10 μA to the SF stage and 5.8 μA to the opamp, givinga total quiescent current consumption of 98.4 μA.The layout is presented in Fig. 4 and has been designed foroptimized chip area and measures 150 μm x 42 μm. Commoncentroid matching and dummy devices have been used wherenecessary and possible. Due to the extremely low W/L ofthe devices in the opamp, it has not been possible to use unittransistors in the design. The enormous transistor in the leftpart is Q1 with dimensions 3000μm/0.7μm.TABLE I: Device dimensions and drain currentDevice Width [μm] Length [μm] Iquiescent [μA]Q1 3000 0.7 10Q2 84 0.7 82.2Q3 140 0.6 82.2Q11,12 1 1 0.075Q13,14 0.5 4 0.075Q15 0.5 1 0.15Q16 30 1 5.5Q17 5 1 5.5Q18 0.5 1 0.15Fig. 4: Screenshot of the layout of the proposed linear regulatorPost-layout simulation has been performed to account forparasitic components in the layout. The frequency responsesof the individual circuit segments and the closed loop gainare depicted on Figs. 3a and 3b. It appears that loadingthe linear regulator by 20 pF will result in an underdampedresponse due to a phase margin of around 30 degrees. Atransient analysis has been performed on schematic and thepost-simulated layout level. The circuit was tested with acurrent step load of 0-50 mA with a rise -and fall time of1 μs. The transient performance is showed on Fig. 4. Whensimulating with the extracted parasitics, the transient responseexhibit a larger and longer voltage drop during transitionsin the current step load. This drop might be caused by thecapacitance between the metal layers and poly covering thelarge drain-source and gate area of Q1 respectively. It shouldbe noted that the size of the current step represents a worstcase scenario. Under typical circumstances smaller load stepsare expected. When a 20 pF load is applied, oscillations occurduring step down of IL. Referring to Fig. 3b, this responseis expected due to the low phase margin. The oscillationsonly occur during load stepdown because gm1 decreases withthe current in Q1 and thereby moves ωp2 down in frequencyaccording to (3). A higher immunity to CL is conclusivelyobtained with a greater gm1. A TR of 39 ns is obtained fromthe schematic level simulations. When simulating with theextracted parasitics included TR increases to 1.158 μs. This is asigniﬁcant difference that indicates layout improvements couldbetter the performance. The voltage undershoot is 140 mV forthe schematic and 160 mV for the layout. If the duration of theload step is reduced to 10 ns, a TR of 20.4 ns is obtained witha 640 mV undershoot on schematic level. Simulations showedthat rise times of the load step greater than 1 μs would resultin even lower undershoot voltages.IV. DISCUSSIONThe presented theory and results of the proposed linearvoltage regulator show that an bulky external capacitor can bereplaced by a fast control loop. Due to the sensitivity to largerload capacitances, the regulator should supply internal circuitryonly. The chip area of the proposed design is fairly small whencomparing to the other designs in Table II. Also the design issimple to implement, which makes it ideal for a system-on-chip designs. The simulation results from the schematic leveland extracted layout simulations of the proposed design aresummarized in Table II for comparison with other designs.A ﬁgure of merit (FOM) from [1] is used for standardizedcomparison and appears in (5). As seen, (5) focuses on howTABLE II: Comparison with other designs[1] [4] [3] This workSchematic LayoutActive area 0.0040 mm2 - 0.08 mm2 - 0.0093 mm2Supply 1.2 V - 1.8 V/3.6 V 3.3 V 3.3 VOutput 0.9 V 2.5 V 1.2 V 1.8 V 1.8 VIquiescent 6 mA 80 uA 132 uA 98.4 uA 98.3 uAImax 100 mA 100 mA 200 mA 50 mA 50 mAIL Rise time 100 ps 10 us 1 us 1 us 1 usTR 0.54 ns 15 us 200 ns 39 ns 1.16 μsUndershoot 90 mV 60 mV 16 mV 140 mV 160 mVFOM 0.032 ns 11.2 ns 0.132 ns 0.077 ns 2.281 nsDecoupling 0.6 nF - - - -fast a system can be made with a certain current efﬁciency.The smaller the FOM, the better the regulator.FOM = TRIquiescentIL,max(5)The chip area consumed by this design is considerably smallerthan [3] and comparable with [1]. Assuming the layout wasoptimized and matched the performance on schematic level,the results of this work show a promising performance interms of FOM compared to [4] and [3]. This topology canalso be designed to drive greater capacitive loads which canbe achieved by increasing the current in Q1 for a higher gm1.V. CONCLUSIONA new capacitor-free linear voltage regulator utilizingmulti-loop control, suited for small system-on-chip applica-tions, was designed. With its fast transient performance itdemonstrated results comparable to or better than other similardesigns from the literature. Simulation results showed that anundershoot of 140 mV with a rise time of 39 ns occured whena 1 μs load transient variation from 0-50 mA was applied.REFERENCES[1] P. Hazucha, T. Karnik, B. Bloechel, C. Parsons, D. Finan, and S. Borkar,“Area-efﬁcient linear regulator with ultra-fast load regulation,” IEEE J.Solid-State Circuits, vol. 40(4), pp. 933–940, 2005.[2] “Selecting LDO regulators for cellphone designs,” Maxim, 2001, appli-cation note 898.[3] T. Jackum, G. Maderbacher, W. Pribyl, and R. Riederer, “Fast transientresponse capacitor-free linear voltage regulator in 65nm cmos,” inProceedings - IEEE International Symposium on Circuits and Systems,2011, pp. 905–908.[4] M. Loikkanen and J. Kostamovaara, “A capacitor-free cmos low-dropoutregulator,” in Proceedings - IEEE International Symposium on Circuitsand Systems, 2007, pp. 1915–1918.[5] X. Tang and L. He, “Capacitor-free, fast transient response cmos low-dropout regulator with multiple-loop control,” in Proceedings of Inter-national Conference on Asic, 2011, pp. 104–107.

A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOS

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A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOS

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