Process Optimization of Dielectric CVD Film for Patterning Related Defect Reduction at 28nm Technology

Abstract

As semiconductor device scales down towards 28nm technology and below, patterning technique becomes more critical and challenging to achieve circuit image with more stringent features, especilly for critical layers, such as AA, Gate, CT and M1 etc. Good patterning performance is not only related to lithograph/etch process window, but also process variation of various patterning related films, such as surface roughness, defect density and size, etc. In this paper, a few patterning related dielectric films, including APF (Advanced Patterning Film), NF-DARC (Nitrogen Free Dielectric Anti-Reflective Coating) and hardmask oxide/nitride, were discussed on defect reduction in a 28nm logic chip. Four types of patterning related defects at AA, CT and Gate layer, were addressed, which are Si cone, CT missing/distortion, poly bridging and tiny abnormal poly pattern. An in-depth study of defect source and mechanism of defect formation and transformation were dicussed. Potential solutions involving improved DCVD film deposition processes were also presented.</jats:p