A 190 x 244 element charge coupled area image sensor has been designed, fabricated and tested. This sensor employs an interline transfer organization and buried n-channel technology. It features a novel on-chip charge integrator and a distributed floating gate amplifier for high and low light level applications. The X-Y element count has been chosen to establish the capability of producing an NTSC compatible video signal. The array size is also compatible with the Super 8 lens format. The first few sample devices have been successfully operated at full video bandwidth for both high and low light levels with the charge amplifier system

Walsh, L. R.

English

NASA Technical Reports Server

A 190 X 244 CHARGE-COUPLED AREA UlIAGE SENSOR 
WITH INTERLINE TRANSFER ORGANIZATION 
L. R. Walsh 
Fairchild Camera and Instrument 'Corporation 
Research and Development Laboratory 
Palo Alto, California 
A 190 X 244 element charge-coupled area image 
sensor has been designed, fabricated and tested. This 
sensor employs an interline transfer organization and 
buried n-channel technology. It features a novel on- 
chip charge integrator and a distributed floating-gate 
amplifier for high and low light level applications. 
The X-Y element count has been chosen to establish 
the capability of producing an  NTSC-compatible video 
signal. 
Super-8 lens format. 
The a r ray  size is also compatible with the 
The first few sample devices have been suc- 
cessfully operated at full video bandwidth for both 
high and low light levels with the charge amplifier 
sy s tem. 
I. DEVICE ARCHITECTURE 
The successful development at Fairchild in  1973 of the CCD-201, a 100 X 
100 element CCD area imaging device, led to the decision to follow it with a 
larger structure based on essentially the same design philosophy. 
is a 190 X 244 element buried-channel charge-coupled area imager designed 
with interline transfer organization and using topside illumination. 
count on the 190 X 244 was chosen to establish compatibility with the Fairchild 
type 3261 sync generator in order to facilitate the generation of TV compatible 
video. The X-Y format was selected to approximate that of the Super-8 movie 
camera. 
a r ea  is photosensitive. 
This device 
The element 
With the interline transfer organization employed, 50% of the imaging 
137 
https://ntrs.nasa.gov/search.jsp?R=19750020763 2020-03-22T19:54:03+00:00Z
Figure 1 shows a functional layout of the device. The area array portion 
is similar in architecture to that of the CCD-201, except for the number of ele- 
ments involved and a higher packing density. 
columns in the array, one corresponding to each column of photosensors. 
vertical registers a r e  of the 24, implanted barr ier  type. Their outputs parallel- 
couple into a high-speed output register which drives the amplifier system. 
Another high-speed register is located at the opposite end of the a rea  array and 
permits the circulation of electrical information through the array. 
input and output registers are of the four-phase type. 
There are 190 vertical register 
The 
Both the 
The amplifier section contains four separate amplifiers, enabling one to 
make sensitive performance comparisons between them. 
(1) a gated charge integrator (GCI), (2) a distributed floating-gate amplifier 
(DFGA), (3 )  an  input floating-gate amplifier (FGA1) located at  the input to the 
DFGA and (4) an output floating-gate amplifier (FGAZ) located at the end of the 
input channel of the DFGA. 
at the input to the GCI and the other at the floating-gate devices so that the array 
output can be channeled through either system. 
These amplifiers a r e  
There a re  two charge steering gates, one located 
A view of the 190 X 244 die is shown in  Figure 2. It contains 33  bonding 
pads. 
operating flexibility for the evaluation of the amplifiers. 
242 mils. 
sions to 5250 mils so that the masks would not have to be photocomposed. 
resulted in  the necessity to fold back the output register so that the amplifiers 
used space in  the Y direction. 
The pad count is not minimal but reflects the desire to have maximum 
The die size is 248 x 
One of the design objectives was to constrain both the X and Y dimen- 
This 
Figure 3 shows the portion of the output register which interfaces with the 
amplifier structure. 
frame time and moved to vertical register sites 'B' during one field and to 
sites 'C' during the next field. 
taneously, transferring a row of data to the output register at the end of each 
horizontal scanning line. 
Photo car r ie rs  are integrated a t  photosites 'A' for one 
All vertical register columns a r e  clocked simul- 
II. AMPLIFLER DESIGN - 
In Figure 3, two separate control gates a re  shown (shaded) which enable 
one to direct charges either to the GCI o r  to the DFGA channel itself. 
channel was made approximately half the size of the output channel so that 
This 
138 
noise could be minimized. This sacrifice in charge handling ability was justified 
on the basis that the DFGA is primarily designed for low light level operation. A 
useful feature of this layout is that excess charge occurring while the DFGA is 
being used can be drained off to the GCI; therefore the GCI can function as a sat- 
uration control. Also it should be noted that DFGA analysis can be facilitated by 
injecting signals electrically into the DFGA through .the reset  circuit. 
The GCI structure consists of an MOS signal amplifier and a reset  circuit 
for resetting the amplifier gate after each charge packet has been sampled. 
addition, there is a compensation amplifier, which does not receive the signal 
but is subjected to the reset  transients seen by the signal amplifier. 
the difference between the two outputs in  an external amplifier, reset  transients 
can be suppressed. 
In 
By taking 
The theory and operation of the DFGA have been discussed previously 
(Ref. 1). In summary, the operation of a single floating-gate amplifier is 
based on the principle that the signal charge of a CCD channel can be nondestruc- 
tively sensed by a floating-gate electrode. 
fier, the same signal charge is repeatedly sensed, thereby increasing the 
signal-to-noise power ratio by a factor equal to the number of times it is 
detected. 
In a distributed floating-gate ampli- 
Figure 4 shows a view of the floating-gate amplifier system. Charge 
packets a r e  transferred into the floating-gate input channel from the area a r r a y  
output register where they a re  first  sensed by FGA1. 
through the input channel, they a r e  subsequently sensed by the 12 floating-gate 
structures associated with the DFGA. 
single floating-gate amplifier (FGAZ) and then terminate in  a sink at the end of 
the channel. 
As they a re  clocked 
Finally, they a re  detected by another 
Each of the twelve floating gates modulates its source-drain current, 
which flows under the large gates in the DFGA output channel. Charges clocked 
through the output channel a r e  detected by a large floating gate a t  the end, which 
couples it to a large single floating-gate amplifier, designated FGA3. The cur- 
rent which flows into the output channel i s  under the control of a gate clocked at  
the data rate running between the two. Adjacent to it i s  a second gate, which i s  
dc biased to reduce transient coupling from the clocked gate to the input channel. 
139 
III. PHOTOCELL DESIGN 
A plan view and cross-section through a typical cell of the a rea  array are 
shown in Figure 5. 
region and on the fourth by a barr ier  controlled by the vertical clock phases. 
Running vertically over columns of photosites is a first polysilicon layer, the 
photogate, which performs the car r ie r  integration function and is clocked at the 
fraxne rate. 
terized by a carr ier  storage region bounded by channel stops and by gated bar-  
riers. Transfer in and out of a vertical cell is controlled by a gate made from 
a second polysilicon layer and clocked at the television scanning rate. 
A photosite is defined on three sides by a Pt  cha 
Adjacent to each photosite is a vertical shift register cell, charac- 
The signal saturation charge level for the cell i s  0.07 pc, based on barr ier  
heights of 3 volts. 
time constant of 120 nsec. 
with a time constant of 230 nsec. 
The photogate has a terminal capacitance of 2200 pF and a 
The total capacitance of the vertical gates is 1500 pF 
IV. STRUCTURAL DETAILS 
In the fabrication of the device, nine mask levels a r e  involved. As Fig- 
ure 4 indicates, the surface topography consists of two polysilicon layers with 
silicon nitride and thermal oxide dielectrics insulating them from each other 
and from the substrate. 
aluminum, which in the area a r ray  serves to opaque the vertical registers. 
The vapox dielectric functions a s  a substrate for the 
In fabricating the device, the most critical process steps a r e  the two 
masking operations, where the horizontal register gate structures a re  defined. 
The major phases, +, and +H2, a r e  formed from the first polysilicon layer, 
while the minor phases, +H3 and +H4, a re  made from the second polysilicon 
layer. The overlap between the two sets of gates is 2 pm, which is the mini- 
mum design rule tolerance for all layers. 
The definition of the floating-gate structure in the DFGA is also critical. 
In order to maximize sensitivity, the capacitance of the floating gates must be 
kept low. In this design, they are 5 pm wide and are defined in the f i rs t  poly. 
The phase gates on either side of them a r e  defined in the second poly and 
should ideally be positioned so that there is no gap on either side of the floating 
gates. 
3 pm.at this point. 
This requirement results in a separation between the phase gates of 
140 
In contrast to the etched gate structures which form the photogate and 
horizontal register gates, the vertical gates are formed by selectively doping 
the second polysilicon layer. 
with undoped poly. 
Thus the gaps between vertical gates a r e  bridged 
V. DRIVE CONSIDERATIONS 
The input register, output register and DFaA are driven from the same 
four-phase clocking circuit. 
array, another line can be clocked in. 
horizontal line. 
output. 
necting channel. 
therefore 190 f 43 = 233. 
While a line of information is clocked out of the 
There are 190 information bits in  each 
The longest path from the output register is that to the DFGA 
There a r e  24 transfers for each phase in the DFGA, and 19 in the con- 
The total number of high-speed transfers for each phase is  
For  a horizontal clock rate of 7.16 MHz, the element time is 140 nsec; 
thus'the high-speed sections a r e  emptied in 32.6 psec. 
interval is  63. 5 psec for standard TV,  the inhibit time is 30. 9 psec. 
horizontal registers can be clocked in either a two- or  four-phase mode. 
Since the horizontal 
The 
In the vertical registers,  there is  a vertical gate per sensor row, i. e . ,  
244, plus three extra to allow for the incorporation of circuitry at either end. 
The vertical clock rate  is  15.75 kHz for a scan time of 15 .6  msec/field and a 
vertical inhibit time of 1. 07 msec (60-Hz field rate). 
Figure 6 shows a four-phase timing diagram suitable for driving the 
device. In this implementation, 260 CCD bit pulses a r e  generated. 
horizontal inhibit period, all horizontal phases except 4Hl a r e  kept low until 
the next line of video has been transferred in from V 
this time. 
field. 
During the 
which i s  also low at 
One hundred and twenty-eight vertical pulses a r e  generated per 
1' 
One hundred and twenty-three a r e  needed a s  a minimum. 
Charges a r e  transferred from the area a r ray  to the output register 
during the horizontal inhibit interval, and from the photosites to the vertical 
registers during the vertical inhibit interval, 
VI. PERFORMANCE 
A number of 190 X 244 runs have been successfully fabricated to date. Good 
high light level imaging has been demonstrated. 
utility of the DFGA for the detection of signal levels on the order of 30 electrons 
has been confirmed. Figure 7 shows high light level images from the DFGA and 
At very low light levels, the 
141 
FGAl. 
of the area a r ray .  When all on-chip output amplifiers are biased as source fol- 
lowers with RS = 1 K ,  typical saturation output voltages are 30 mV for the GCI, 
FGAl and FGAZ, and 150 mV for the DFGA. These pictures were taken at data 
rates of 10 MHz. Horizontal 
resolution is approximately 142 lines/picture height. Vertical resolution is 
approximately 244 lines/picture height. 
The DFGA can handle approximately 90% of the saturation charge level 
Transfer inefficiency is negligible to 20 MHz. 
Representative low light level images a re  shown in Figure 8. Here the 
DFGA output is being viewed at five different light levels, at a date rate of 
10 MHz, and in a +25"C ambient. 
approximately 140,000 electrons. 
was attenuated using neutral density filters, the final attenuation resulting in 
an image of about 70 electrons. 
Figure 8a shows a high light level image of 
In the subsequent pictures, the light source 
VII. SUMMARY 
A 190 X 244 CCD buried-channel a rea  imaging a r r ay  has been developed. 
An on- chip 12- stage distributed floating-gate amplifier significantly enhances 
the detectability of low light level images. Good a r r ay  performance has been 
achieved at data rates up to 20 MHz. 
ACKNOWLEDGEMENT 
The development of this imaging a r r ay  was in part  supported by the Naval 
Electronic Systems Command. 
REFERENCE 
1. D. D. Wen, "A Distributed Floating Gate Amplifier in Charge Coupled 
Devices," ISSCC, 1975. 
142 
+, 
3 
0 c 
.--( 
3 
M 
iz 
143 
Figure 2, Photograph of die 
144 
fl 
SIGNAL r 
AMP AMP 
CONTROL 
GATE TO F 
SYSTEM 
Figure 3. Detail view of array at amplifier interface 
145 
Figure 4. Floating-gate amplifier system 
146 
ALUMINUM - f 
THERMAL 
IMPLANTED BURIED CHA GATE OXIDE 
LAYER 
Figure 5. Cell structure in area array 
+P lJ-------lJ-- 
For 29  operotion, ond +Hs 0r0 in P~OMJ; also 4H2 is in 
phasa with 4 ~ 4  
Figure 6. Timing diagram 
147 
I 
, 
Figure 7. High light level images from 
(a) the DFGA and (b) FGAl (To read 
the effective resolution, divide the test 
chart numbers by two. ) 
148 
f b )  ND= 9.0, 14,000 electrons ( d )  ND=3.0, 140 electrons 
( a )  ND=O, 140,000 electrons 
( c )  ND=2.0, 1400 electrons Dt3.3,  70 electrons 
Figure 8.  DFGA images at t25"C ambient, showing the effect of progressive 
light attenuation on image quality 
149 


A 190 by 244 charge-coupled area image sensor with interline transfer organization

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