Data for the beam-leaded silicon-on-sapphire (SOS) process using the TA5388 dual-complementary pair plus inverted circuit show the stability of the dc device characteristics through the complete beam-lead processing and packaging steps. A more complex circuit, the TA6567 - a silicon-gate, voltage-sense BL/CMOS/SOS 256-bit RAM, has also been made that was functionally perfect at wafer probe. Efforts to increase the yield of this circuit and to obtain electrically perfect packaged units are discussed

Schneider, W. C.

English

NASA Technical Reports Server

DESIGN, PROCESSING, AND TESTING
OF LSI ARRAYS FOR SPACE STATION
BY
c NW. C. SCHNEIDER
QUARTERLY TECHNICAL REPORT NO. 16
MARCH 1975
Q E-1I)O
o() U Distribution of this report is provided in the interest
U U of information exchange and should not be construed
O4 - as endorsement by NASA of the material presented.
S Responsibility for the contents resides with the
41 .*4 organization that prepared it.
S0RCA LABORATORIES
HUNTSVILLE, ALABAMA 35812
W ;P4 44
v U U PREPARED UNDER CONTRACT NO. NAS12-2207 BY
N E-4 0 RCA LABORATORIES
N P4. PRINCETON, NEW JERSEY 08540
https://ntrs.nasa.gov/search.jsp?R=19750013449 2020-03-22T23:32:38+00:00Z
1. Report No. 2. Government Accession No. 3. Recipient's Catalog No.
4. Title and Subtitle 5. Report Date
March 1975DESIGN, PROCESSING, AND TESTING OF 6. Performing Organization Code
LSI ARRAYS FOR SPACE STATION
7. Author(s) 8. Performing Organization Report No.
W. C. Schneider PRRL-75-CR-20
9. Performing Organization Name and Address 10. Work Unit No.
RCA Laboratories
Princeton, NJ 08540 11. Contract or Grant No.
NAS12-2207
13. Type of Report and Period Covered
12. Sponsoring Agency Name and Address Qtly .Tech.Report No. 16
George C. Marshall Space Flight Center (10/1/74 to 12/31/74)
National Aeronautics & Space Administration 14. Sponsoring Agency Code
Huntsville, Alabama 35812
15. Supplementary Notes
16. Abstract
Data for the beam-leaded SOS process using the TA5388 dual-
complementary pair plus inverted circuit show the stability of the
dc device characteristics through the complete beam-lead processing
and packaging steps. A more complex circuit, the TA6567 - a silicon-
gate, voltage-sense BL/CMOS/SOS 256-bit RAM, has also been made that
was functionally perfect at wafer probe. Current efforts are to in-
crease the yield of this circuit and to obtain electrically perfect
packaged units.
17. Key Words (Selected by Author(s)) 18. Distribution Statement
Random access memory (RAM)
Beam-lead process
19. Security Classif. (of this report) 20. Security Classif. (of this page) 21. No. of Pages 22. Price
Unclassified Unclassified 18
*For sale by National Technical Information Service, Springfield, Virginia 22151.
TABLE OF CONTENTS
Section Page
SUMMARY . . . . .. . . . . . . . . . .. . . . . . . . . . . . . 1
I. INTRODUCTION .... .. . . .. . . ... . . . . . . . . . . . 2
II. PROCESSING PROBLEMS WITH BL/SOS TA6567 256-BIT RAM . .... 3
III. BEAM-LEADED SOS PUSH-OFF TESTS . . . .... . . .... . . . ... 5
IV. ELECTRICAL RESULTS ON PACKAGED BEAM-LEADED SOS DEVICES . . . 6
V. PERSONNEL AND EXPENDITURES . . ... .... .. . ... . . 11
VI. NEW TECHNOLOGY APPENDIX. . . . . ............ . . 12
ACKNOWLEDGMENTS . . . . . . . . . ... .. . . . . . . . . . . 13
REFERENCES . ............ . . . . . .... . . . . . . 14
iii
LIST OF ILLUSTRATIONS
Figure Page
1. Contact opening and metal coverage on the TA6567 circuit . 3
2. VTN values of TA5388 BL/SOS packaged units from SW27-1,
500-X Si3N 4 .  . . . . .. . .. . . .. . . . . . . .  9
3. VTP values of TA5388 BL/SOS packaged units from SW27-1,
500-X Si3N4 . . .  . . . . . . . ..  . . . . . . . . .. 10
iv
DESIGN, PROCESSING AND ^ TESTING OF LSI ARRAYS
FOR SPACE STATION
by
W. C. Schneider
RCA Laboratories
Princeton, New Jersey
SUMMARY
Data for the beam-leaded SOS process using the TA5388 dual-comple-
mentary pair plus inverted circuit show the stability of the dc device
characteristics through the complete beam-lead processing and packaging
steps. A more complex circuit, the TA6567 - a silicon-gate, voltage-
sense BL/CMOS/SOS 256-bit RAM, has also been made that was functionally
perfect at wafer probe. Current efforts are to increase the yield of
this circuit and to obtain electrically perfect packaged units.
I. 'INTRODUCTION
The evolution of the SOS technology at RCA has covered a broad
spectrum of research and development into basic materials, and device
research and advanced CMOS LSI techniques including computer-aided de-
sign, mask-making, circuit design, and processing. The present NASA
contract has given partial support to this effort to develop a beam-
leaded (BL) silicon-gate CMOS/SOS technology with the 256-word by 1-bit
RAM as the demonstration vehicle.
The circuit design and basic processing evolved from an aluminum-
gate process to a silicon-gate process and finally included the beam-
leads. The beam-lead process incorporated a modified micro-bridg-
approach to form the beams on.SOS and a novel approach to laser-scribing
to successfully separate the chips.
Initial beam-lead development was done on the TA5388 dual-comple-
mentary pair plus inverter circuit. The 256-word BL/SOS RAM unit, the
TA6567, was demonstrated functionally perfect at wafer probe but with
low yield. No perfect packaged.TA6567 units have been made, but some
processing problems have been defined which could affect the yield.
2
II. PROCESSING PROBLEMS WITH BL/SOS TA6567 256-BIT RAM
In general, the major processing problems were defined and resolved
for the beam-leaded SOS processing by using the TA5388 dual-complementary
pair plus inverted circuit. Data have been given (Ref. 1 and this report)
to show that good electrical results were obtained on this simple circuit.
Certain processing problems can be expected to arise when a more complex
circuit with more stringent design rules is substituted. One such prob-
lem was encountered in the BL processing of the TA6567 circuit. The diffi-
culty is basically overetching the contacts and hence not getting complete
coverage of metal over the contact area or junction passivation.
Figure 1 shows an area of the TA6567 with overetched contacts and
the metal that does not completely cover the contact area. This in-
vites a problem of inadequate passivation and possible contamination
Figure 1. Contact opening and metal coverage
on the TA6567 circuit.
3
of the device silicon during the beam-lead processing. The larger con-
tacts in this circuit were designed as 0.2 mil wide and measure 0.3 mil
wide, and the 0.5-mil metal measured 0.45 to 0.48 mil wide. This prob-
lem becomes more serious when we attempt to align all the chips across
a 2-in.-diameter wafer. The overetching is more likely to happen with
the beam-lead processing because the contact etching requires etching
through the Si3N4 passivation layer as well as the SiO 2 layer, thus in-
creasing the chance of undercutting and enlarging the contact area.
Two solutions to this problem are being explored. First, we are
trying for better control of the contact dimensions by improving the etch-
ing techniques. Second, for the same purpose, a new contact mask with
smaller dimensions will be available shortly.
4
III. BEAM-LEADED'SOS PUSH-OFF TESTS
A measure of the mechanical strength of the beam-leaded TA5388 SOS
chips was made using the standard push-off test. This test involves
bonding the beam-leaded chip to a metallized ceramic and measuring the
force necessary to cause mechanical failure of the bonds. The force is
applied by a plunger passing through a hole in the ceramic to the cir-
cuit area of the pellet. The data presented in Table 1 are in 'grams'
of push-off strength and the general type of failure observed. The
bottom line of Table 1 gives data for a 14-lead BL bulk chip for com-
parison with the BL/SOS. The 'Location of Failure' refers only to the
general area of failure in the bulk because of the differences between
bulk and SOS BL processing.
Table 1. 14-Lead Beam-Lead SOS Push-Off Test Failures
Number of Failures 'grams'
Location of Beam-to- Beam at Base Metal (Au I) Broken Push-off
Failure Substrate Metal Pillar to Beam (Au II) Beam Strength
Wafer No.
SW27-1 33 16 3 6 69
SW28-3 40 11 3 - 53
Master
5959 4 2 55 7 83
It should be emphasized that these values are from initial tests on
the BL/SOS devices and that the processing has not been optimized for
beam strength.
The predominant BL/SOS failure mechanism is the beam-to-substrate
bond; it differs from the bulk-failure mechanism. The push-off strength
values for the SOS are well above the minimum acceptable strength of 32
grams for a 14-lead device. Again, the SOS processing is not optimized
and the SOS push-off strength is lower than the bulk push-off strength.
5
IV. ELECTRICAL RESULTS ON PACKAGED BEAM-LEADED SOS DEVICES
The discussion of electrical results in this section is a.continua-
tion of the experiment using the TA5388 circuit, as described in the
previous report [Ref. 1]. The data presented in that report compared the
TA5388 wafer probe average dc device parameters after the base metal
processing and after the beam formation with the aluminum metal control
wafers for various thicknesses of the Si3N 4 passivation layer. This
update is to check the effect of laser-scribing, separating, and pack-
aging on the device parameters. The data are presented in Table 2 for
the TA5388 circuits at wafer probe and after packaging. For ease of
comparison the wafer probe data labeled Au I and Au II are repeated from
Ref. 1. The data for 1200 X of Si3N 4 are omitted because too few chips
from this wafer were packaged.
The parameters are leakage current (IL) measured in nA/mil, thresh-
old voltage (VT) at 10 pA in volts, transconductance (gm) in pmhos, and
source-to-drain breakdown voltage (VBD) in volts, measured at 50 pA.
The subscripts P and N are for the PMOS and NMOS transistors, respec-
tively. The alphanumeric designation for the wafer is given in paren-
theses on the left of the ILP values. The values for the other device
parameters are listed in the same order as for ILp.
The histograms of VT for wafer SW27-1 of both the NMOST- and
PMOST-packaged devices are shown in Figs. 2 and 3, respectively, and
agree closely with those published as Figs. 12 and 3 in Ref. 1 for Au I
and Au II wafer probe.
The comparison of the data in Table 2 with these histograms shows
that the dc device parameters are not changed drastically through the
entire beam-lead processing and packaging steps.
The first lot of beam-leaded packaged TA6567 circuits, the
BL/SOS/CMOS 256-word by 1-bit RAM, was completed and is undergoing ex-
tensive electrical testing. Initial testing of the first packaged units
shows that the circuit is functioning but generally not as well as it did
6
Table 2. BL/SOS TA5388 Average DC Device Parameters,
VDD = 10 Volts
Wafer Probe
Si3N4  Packaged
Thickness (2) Au I Au II Au II
ILP 500 (SW27-1) 0.8 (SW27-1) 0.9 1.19
(nA/mil) 2000 (SW28-3) 0.7 (SW28-3) 1.0 0.40
ILN 500 -0.7 -0.6 
0.81
(nA/mil) 2000 -3.9 -2.9 4.1
VTp 500 -0.86 -0.84 -0.82
(volts) 2000 -0.87 -0.87 -0.81
@ 50 iA
VTN 500 1.53 1.55 1.57
(volts) 2000 1.41 1.19 1.44
gmP 500 1164 1177 1195
(pmhos) 2000 1240 1245 1176
gmN 500 768 760 760
(pmhos) 2000 950 910 813
VBD(P) 500 
-29.0 
-28.9 29.5
(volts) 2000 -28.1 -27.5 27.1
@ 50 PA
VBD(N) 500 25.8 25.8 25.9
(volts) 2000 26.2 26.5 25.1
at wafer probe. The total circuit current has increased compared with
the value measured at wafer probe, and the cause is being investigated.
The initial measurement of the read access time as a function of output
load capacitance on these units compares closely with the data measured
7
for this circuit with aluminum'metal, as was expected (see page 31,
Ref. 1).
Efforts to improve the yield and obtain more packaged TA6567s for
evaluation are under way. A description of processing problems is given
in Section III of this report.
8
/i-/ 18:55:37
... *.... 4.....4... 4..... .. * .......**...
100 +*
90 * VT NMOS + UPPER LIMIT
+ . 5000E+01
ICBL374 SW271001 +
+
80 + OVER UPPER
+ 0
c * +4 * uNOER LOWEA
++ . 0
++
50 + ++ + + +, TOTAL: 20
+ ++ + ++
40 + * + ++ LARGEST: 4
+ ++ ++ ++
4 4 44 .4 4* LA RS
+ ++ + + +
4 + ++ + + 4S ++
S++++ + 4 +
+++++ + + + + +++ ++ + +++  ..156 1
+++++++ +
20 +++++ * + + + ++ EN
10+++*+ + + + + +++ . .15676+01
++++ + + + + ++ +++
+++++++ + + + ++ ++++
+++++++ + + ++ ++++
+++++ + + + + ++ ++ .155sO*+O
+++++ + + + ++ ++++
+++++ + es ++++
0 +..4....4....4................*** * ** * ** **.** **
.5 .0 .7 .a .9 .1 .1 .L .1 .1 . .1 .1 .1 . 2 .2 .2 .2 .2
500 500 500 500 500 (50 1?0 250 3(, 453 550 oS3 75J 35v q5L 35 J 15 25j 35( 450
+00 +00 00 +03 uO + 0 +I *i +01 ,OL +vul +t +, t+u +0 +u +0i +01 +Gi +0
%o Figure 2. VTN values of TA5388 BL/SOS packaged units from SW27-1, 500-R Si3N 4.
o I1-I 18:55:33
100 * *
90 * + * UPPER LIMIT
+ •
80 * VT PMOS 4 * 0 OVER UPPER
. 0
ICBL374 SW271001 ..
4
c0 70* + * LOWER LIMIT
4 . -. 000E+
b0 O * * _UNDER LQMUlER_+ _
50 * TOTAL: 27
+++
30 * +++ 0# BARS 100
+++
20 * +* _REAN
4 +44+ . -. 83429E*o00
+ +++
10 * 4 ++++ * SIGMA
*++ .++++++ . 79391E-01
++ +++ ++
++ ++++++
-. 2 -. Z -. 1 -. 1 -. 1 -. 1 -.2 -. -,t -. I -. 1 -. 1 -. 9 -. d -. 7 -. o -. 5 -. 4 -. 3 -. 2
150 050 950 350 75u 65u 50 450 350 250 150 050- 500 500 500 500 500 500 !CU 500
+01 +01 +01 +01 +01 +V1 +01 +01 +( +UL +01 + +00 •Ob +0o +O 00 +00 +00 +00 +00
Figure 3. VTp values of TA5388 BL/SOS packaged units from SW27-1 500-a Si3N 4 .
Fiur 34 VTP S'3
V. PERSONNEL AND EXPENDITURES
During the quarter (10/1/74 to 12/31/74) reported herein the follow-
ing personnel contributed to the contract:
W. C. Schneider Project Scientist
Total expenditures through December 31, 1974 have been $256,648,
including profit. Problem areas that may create an overrun: none at
this time.
11
VI. NEW TECHNOLOGY APPENDIX
It was concluded from the review of the work that there were no
reportable items of New Technology under the contract during the period
covered by this report.
12
ACKNOWLEPGMENl S
The author wishes to acknowledge the informative discussions with
R. J. Hollingsworth and the processing help given by D. Tanguay.
13
,PEFERENCES
1. W. C. Schneider, Design, Processing, and Testing of LSI Arrays for
Space Station, Quarterly Technical Report No. 15, Contract
NAS12-2207, November 1974.
14


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